Datasheet AD7173-8 (Analog Devices)
| Manufacturer | Analog Devices |
| Description | Low Power, 8-/16-Channel, 31.25 kSPS, 24-Bit, Highly Integrated Sigma-Delta ADC |
| Pages / Page | 64 / 1 — Low Power, 8-/16-Channel, 31.25 kSPS,. 24-Bit, Highly Integrated … |
| Revision | B |
| File Format / Size | PDF / 1.2 Mb |
| Document Language | English |
Low Power, 8-/16-Channel, 31.25 kSPS,. 24-Bit, Highly Integrated Sigma-Delta ADC. Data Sheet. AD7173-8. FEATURES. APPLICATIONS
Model Line for this Datasheet
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Low Power, 8-/16-Channel, 31.25 kSPS, 24-Bit, Highly Integrated Sigma-Delta ADC Data Sheet AD7173-8 FEATURES APPLICATIONS Low power, 8-/16-channel, highly integrated multiplexed Process control: PLC/DCS modules analog-to-digital converter (ADC) Voltage, current, temperature, and pressure measurement Integration Flow meters Precision analog input buffers and reference input buffers Medical and scientific multichannel instrumentation 2.5 V precision reference (3.5 ppm/°C) Seismic instrumentation Cross point multiplexer (enable system diagnostic) Chemical analysis instrumentation: chromatography 8 full differential or 16 single-ended channels GENERAL DESCRIPTION Clock oscillator GPIO and GPO pins with automatic external mux control
Fast settling, highly accurate, low power, 8-/16-channel,
Fast and flexible output rate: 1.25 SPS to 31.25 kSPS
multiplexed ADC for low bandwidth input signals with
Channel scan data rate: 6.21 kSPS/channel (161 µs settling)
integrated input buffers.
Performance specifications
Integrated precision, 2.5 V, low drift (3.5 ppm/°C), band gap
17.5 noise free bits at 31.25 kSPS
reference and integrated oscil ator.
24 noise free bits at 1.25 SPS
Eight flexible setups with configurability for output data rate,
INL: ±3 ppm/FSR 85 dB rejection of 50 Hz and 60 Hz with 50 ms settling
digital filter mode, offset/gain error correction, reference selection,
Operates with either 3.3 V or 5 V supply
buffer enables and more. This per channel configurability extends
Single supply
to the output data rate used for each channel when using
3.3 V or 5 V AVDD1, 2 V to 5 V AVDD2, and 2 V to 5 V IOVDD
sinc5 + sinc1 filter.
Optional split supply
Sinc5 + sinc1 filter maximizes channel scan rate, and sinc3 filter
AVDD1 and AVSS ± 2.5 V or AVDD1 and AVSS ± 1.65 V
maximizes resolution and enhanced 50 Hz/60 Hz rejection,
Current: 1.4 mA
with four selectable options to maximize rejection.
3-/4-wire serial digital interface (Schmitt trigger on SCLK)
Integrated diagnostic features, including CRC, register checksum,
CRC error checking
temperature sensor, crosspoint multiplexer, burnout currents,
SPI, QSPI, MICROWIRE, and DSP compatible
and GPIOs/GPOs.
Package: 40-lead 6 mm × 6 mm LFCSP Temperature range: −40°C to +105°C FUNCTIONAL BLOCK DIAGRAM AVDD1 AVDD2 REGCAPA REF– REF+ REFOUT IOVDD REGCAPD BUFFERED 1.8V 1.8V PRECISION LDO LDO REFERENCE REFERENCE CROSSPOINT INPUT MULTIPLEXER BUFFERS INT AIN0/REF2– AVDD REF ANALOG CS INPUT BUFFERS AIN1/REF2+ SCLK SERIAL DIN Σ-Δ ADC DIGITAL INTERFACE FILTER AND CONTROL DOUT/RDY SYNC AIN15 ERROR XTAL AND INTERNAL AVSS I/O AND EXTERNAL AIN16 CLOCK OSCILLATOR MUX CONTROL CIRCUITRY AD7173-8 TEMPERATURE SENSOR
001
AVSS PDSW GPIO0 GPIO1 GPO2 GPO3 XTAL1 XTAL2/CLKIO DGND
1773- 1 Figure 1.
Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2013–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS NOISE PERFORMANCE AND RESOLUTION GETTING STARTED POWER SUPPLIES Single Supply Operation (AVSS = DGND) Split Supply Operation (AVSS ≠ DGND) DIGITAL COMMUNICATION Accessing the ADC Register Map AD7173-8 RESET CONFIGURATION OVERVIEW Channel Configuration Channel Registers ADC Setups Setup Configuration Registers Filter Configuration Registers Offset Registers Gain Registers ADC Mode and Interface Mode Configuration ADC Mode Register Interface Mode Register Understanding Configuration Flexibility CIRCUIT DESCRIPTION ANALOG INPUT Buffered Analog Input Fully Differential Inputs Single-Ended Inputs Buffer Chopping, Noise, and Input Current Running with Single Cycle = 0 Using External Buffers REFERENCE OPTIONS External Reference Internal Reference CLOCK SOURCE Internal Oscillator External Crystal External Clock DIGITAL FILTERS SINC5 + SINC1 FILTER SINC3 FILTER ENHANCED 50 Hz AND 60 Hz REJECTION FILTERS 50 Hz and 60 Hz Rejection Filter Frequency Domain Plots OPERATING MODES CONTINUOUS CONVERSION MODE CONTINUOUS READ MODE SINGLE CONVERSION MODE STANDBY AND POWER-DOWN MODES CALIBRATION MODES DIGITAL INTERFACE CHECKSUM PROTECTION CRC CALCULATION Polynomial Example of a Polynomial CRC Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) XOR Calculation Example of an XOR Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) INTEGRATED FUNCTIONS GENERAL-PURPOSE I/O EXTERNAL MULTIPLEXER CONTROL DELAY 16-BIT/24-BIT CONVERSIONS SERIAL INTERFACE RESET (DOUT_RESET) SYNCHRONIZATION Normal Synchronization Alternate Synchronization ERROR FLAGS ADC_ERROR CRC_ERROR REG_ERROR /ERROR Pin DATA_STAT IOSTRENGTH BIT GROUNDING AND LAYOUT REGISTER SUMMARY REGISTER DETAILS COMMUNICATIONS REGISTER STATUS REGISTER ADC MODE REGISTER INTERFACE MODE REGISTER REGISTER CHECK DATA REGISTER GPIO CONFIGURATION REGISTER ID REGISTER CHANNEL REGISTER 0 CHANNEL REGISTER 1 TO CHANNEL REGISTER 15 SETUP CONFIGURATION REGISTER 0 SETUP CONFIGURATION REGISTER 1 TO SETUP CONFIGURATION REGISTER 7 FILTER CONFIGURATION REGISTER 0 FILTER CONFIGURATION REGISTER 1 TO FILTER CONFIGURATION REGISTER 7 OFFSET REGISTER 0 OFFSET REGISTER 1 TO OFFSET REGISTER 7 GAIN REGISTER 0 GAIN REGISTER 1 TO GAIN REGISTER 7 OUTLINE DIMENSIONS ORDERING GUIDE NOTES
Fast settling, highly accurate, low power, 8-/16-channel,
Fast and flexible output rate: 1.25 SPS to 31.25 kSPS
multiplexed ADC for low bandwidth input signals with
Channel scan data rate: 6.21 kSPS/channel (161 µs settling)
integrated input buffers.
Performance specifications
Integrated precision, 2.5 V, low drift (3.5 ppm/°C), band gap
17.5 noise free bits at 31.25 kSPS
reference and integrated oscil ator.
24 noise free bits at 1.25 SPS
Eight flexible setups with configurability for output data rate,
INL: ±3 ppm/FSR 85 dB rejection of 50 Hz and 60 Hz with 50 ms settling
digital filter mode, offset/gain error correction, reference selection,
Operates with either 3.3 V or 5 V supply
buffer enables and more. This per channel configurability extends
Single supply
to the output data rate used for each channel when using
3.3 V or 5 V AVDD1, 2 V to 5 V AVDD2, and 2 V to 5 V IOVDD
sinc5 + sinc1 filter.
Optional split supply
Sinc5 + sinc1 filter maximizes channel scan rate, and sinc3 filter
AVDD1 and AVSS ± 2.5 V or AVDD1 and AVSS ± 1.65 V
maximizes resolution and enhanced 50 Hz/60 Hz rejection,
Current: 1.4 mA
with four selectable options to maximize rejection.
3-/4-wire serial digital interface (Schmitt trigger on SCLK)
Integrated diagnostic features, including CRC, register checksum,
CRC error checking
temperature sensor, crosspoint multiplexer, burnout currents,
SPI, QSPI, MICROWIRE, and DSP compatible
and GPIOs/GPOs.
Package: 40-lead 6 mm × 6 mm LFCSP Temperature range: −40°C to +105°C FUNCTIONAL BLOCK DIAGRAM AVDD1 AVDD2 REGCAPA REF– REF+ REFOUT IOVDD REGCAPD BUFFERED 1.8V 1.8V PRECISION LDO LDO REFERENCE REFERENCE CROSSPOINT INPUT MULTIPLEXER BUFFERS INT AIN0/REF2– AVDD REF ANALOG CS INPUT BUFFERS AIN1/REF2+ SCLK SERIAL DIN Σ-Δ ADC DIGITAL INTERFACE FILTER AND CONTROL DOUT/RDY SYNC AIN15 ERROR XTAL AND INTERNAL AVSS I/O AND EXTERNAL AIN16 CLOCK OSCILLATOR MUX CONTROL CIRCUITRY AD7173-8 TEMPERATURE SENSOR
001
AVSS PDSW GPIO0 GPIO1 GPO2 GPO3 XTAL1 XTAL2/CLKIO DGND
1773- 1 Figure 1.
Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2013–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS NOISE PERFORMANCE AND RESOLUTION GETTING STARTED POWER SUPPLIES Single Supply Operation (AVSS = DGND) Split Supply Operation (AVSS ≠ DGND) DIGITAL COMMUNICATION Accessing the ADC Register Map AD7173-8 RESET CONFIGURATION OVERVIEW Channel Configuration Channel Registers ADC Setups Setup Configuration Registers Filter Configuration Registers Offset Registers Gain Registers ADC Mode and Interface Mode Configuration ADC Mode Register Interface Mode Register Understanding Configuration Flexibility CIRCUIT DESCRIPTION ANALOG INPUT Buffered Analog Input Fully Differential Inputs Single-Ended Inputs Buffer Chopping, Noise, and Input Current Running with Single Cycle = 0 Using External Buffers REFERENCE OPTIONS External Reference Internal Reference CLOCK SOURCE Internal Oscillator External Crystal External Clock DIGITAL FILTERS SINC5 + SINC1 FILTER SINC3 FILTER ENHANCED 50 Hz AND 60 Hz REJECTION FILTERS 50 Hz and 60 Hz Rejection Filter Frequency Domain Plots OPERATING MODES CONTINUOUS CONVERSION MODE CONTINUOUS READ MODE SINGLE CONVERSION MODE STANDBY AND POWER-DOWN MODES CALIBRATION MODES DIGITAL INTERFACE CHECKSUM PROTECTION CRC CALCULATION Polynomial Example of a Polynomial CRC Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) XOR Calculation Example of an XOR Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) INTEGRATED FUNCTIONS GENERAL-PURPOSE I/O EXTERNAL MULTIPLEXER CONTROL DELAY 16-BIT/24-BIT CONVERSIONS SERIAL INTERFACE RESET (DOUT_RESET) SYNCHRONIZATION Normal Synchronization Alternate Synchronization ERROR FLAGS ADC_ERROR CRC_ERROR REG_ERROR /ERROR Pin DATA_STAT IOSTRENGTH BIT GROUNDING AND LAYOUT REGISTER SUMMARY REGISTER DETAILS COMMUNICATIONS REGISTER STATUS REGISTER ADC MODE REGISTER INTERFACE MODE REGISTER REGISTER CHECK DATA REGISTER GPIO CONFIGURATION REGISTER ID REGISTER CHANNEL REGISTER 0 CHANNEL REGISTER 1 TO CHANNEL REGISTER 15 SETUP CONFIGURATION REGISTER 0 SETUP CONFIGURATION REGISTER 1 TO SETUP CONFIGURATION REGISTER 7 FILTER CONFIGURATION REGISTER 0 FILTER CONFIGURATION REGISTER 1 TO FILTER CONFIGURATION REGISTER 7 OFFSET REGISTER 0 OFFSET REGISTER 1 TO OFFSET REGISTER 7 GAIN REGISTER 0 GAIN REGISTER 1 TO GAIN REGISTER 7 OUTLINE DIMENSIONS ORDERING GUIDE NOTES
