Datasheet AD7173-8 (Analog Devices) - 3
| Manufacturer | Analog Devices |
| Description | Low Power, 8-/16-Channel, 31.25 kSPS, 24-Bit, Highly Integrated Sigma-Delta ADC |
| Pages / Page | 64 / 3 — Data Sheet. AD7173-8. REVISION HISTORY 5/2017—Rev. A to Rev. B. … |
| Revision | B |
| File Format / Size | PDF / 1.2 Mb |
| Document Language | English |
Data Sheet. AD7173-8. REVISION HISTORY 5/2017—Rev. A to Rev. B. 4/2014—Rev. 0 to Rev. A. 10/2013—Revision 0: Initial Version
Model Line for this Datasheet
Text Version of Document
Data Sheet AD7173-8 REVISION HISTORY 5/2017—Rev. A to Rev. B
Changes to Getting Started Section .. 19 Changed LFCSP_WQ to LFCSP ... Throughout Change to Table 11 .. 23 Added Note 1 to Temperature Coefficient Parameter, Table 1 ... 4 Change to Table 17 .. 29 Changes to Power Supplies Section .. 20 Changes to Digital Filters Section ... 31 Added AD7173-8 Reset Section .. 21 Replaced Diagnostics Section with Integrated Function Updated Outline Dimensions .. 63 Section .. 43 Changes to Address 0x02, Table 22... 46
4/2014—Rev. 0 to Rev. A
Changes to Bit 10, Table 26 .. 52 Changes to General Description and Functional Block Changes to Bits[6:5], Table 35 ... 60 Diagram .. 1 Moved Revision History ... 3
10/2013—Revision 0: Initial Version
Changes to Figure 18 .. 14 Rev. B | Page 3 of 64 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS NOISE PERFORMANCE AND RESOLUTION GETTING STARTED POWER SUPPLIES Single Supply Operation (AVSS = DGND) Split Supply Operation (AVSS ≠ DGND) DIGITAL COMMUNICATION Accessing the ADC Register Map AD7173-8 RESET CONFIGURATION OVERVIEW Channel Configuration Channel Registers ADC Setups Setup Configuration Registers Filter Configuration Registers Offset Registers Gain Registers ADC Mode and Interface Mode Configuration ADC Mode Register Interface Mode Register Understanding Configuration Flexibility CIRCUIT DESCRIPTION ANALOG INPUT Buffered Analog Input Fully Differential Inputs Single-Ended Inputs Buffer Chopping, Noise, and Input Current Running with Single Cycle = 0 Using External Buffers REFERENCE OPTIONS External Reference Internal Reference CLOCK SOURCE Internal Oscillator External Crystal External Clock DIGITAL FILTERS SINC5 + SINC1 FILTER SINC3 FILTER ENHANCED 50 Hz AND 60 Hz REJECTION FILTERS 50 Hz and 60 Hz Rejection Filter Frequency Domain Plots OPERATING MODES CONTINUOUS CONVERSION MODE CONTINUOUS READ MODE SINGLE CONVERSION MODE STANDBY AND POWER-DOWN MODES CALIBRATION MODES DIGITAL INTERFACE CHECKSUM PROTECTION CRC CALCULATION Polynomial Example of a Polynomial CRC Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) XOR Calculation Example of an XOR Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) INTEGRATED FUNCTIONS GENERAL-PURPOSE I/O EXTERNAL MULTIPLEXER CONTROL DELAY 16-BIT/24-BIT CONVERSIONS SERIAL INTERFACE RESET (DOUT_RESET) SYNCHRONIZATION Normal Synchronization Alternate Synchronization ERROR FLAGS ADC_ERROR CRC_ERROR REG_ERROR /ERROR Pin DATA_STAT IOSTRENGTH BIT GROUNDING AND LAYOUT REGISTER SUMMARY REGISTER DETAILS COMMUNICATIONS REGISTER STATUS REGISTER ADC MODE REGISTER INTERFACE MODE REGISTER REGISTER CHECK DATA REGISTER GPIO CONFIGURATION REGISTER ID REGISTER CHANNEL REGISTER 0 CHANNEL REGISTER 1 TO CHANNEL REGISTER 15 SETUP CONFIGURATION REGISTER 0 SETUP CONFIGURATION REGISTER 1 TO SETUP CONFIGURATION REGISTER 7 FILTER CONFIGURATION REGISTER 0 FILTER CONFIGURATION REGISTER 1 TO FILTER CONFIGURATION REGISTER 7 OFFSET REGISTER 0 OFFSET REGISTER 1 TO OFFSET REGISTER 7 GAIN REGISTER 0 GAIN REGISTER 1 TO GAIN REGISTER 7 OUTLINE DIMENSIONS ORDERING GUIDE NOTES
Changes to Getting Started Section .. 19 Changed LFCSP_WQ to LFCSP ... Throughout Change to Table 11 .. 23 Added Note 1 to Temperature Coefficient Parameter, Table 1 ... 4 Change to Table 17 .. 29 Changes to Power Supplies Section .. 20 Changes to Digital Filters Section ... 31 Added AD7173-8 Reset Section .. 21 Replaced Diagnostics Section with Integrated Function Updated Outline Dimensions .. 63 Section .. 43 Changes to Address 0x02, Table 22... 46
4/2014—Rev. 0 to Rev. A
Changes to Bit 10, Table 26 .. 52 Changes to General Description and Functional Block Changes to Bits[6:5], Table 35 ... 60 Diagram .. 1 Moved Revision History ... 3
10/2013—Revision 0: Initial Version
Changes to Figure 18 .. 14 Rev. B | Page 3 of 64 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS NOISE PERFORMANCE AND RESOLUTION GETTING STARTED POWER SUPPLIES Single Supply Operation (AVSS = DGND) Split Supply Operation (AVSS ≠ DGND) DIGITAL COMMUNICATION Accessing the ADC Register Map AD7173-8 RESET CONFIGURATION OVERVIEW Channel Configuration Channel Registers ADC Setups Setup Configuration Registers Filter Configuration Registers Offset Registers Gain Registers ADC Mode and Interface Mode Configuration ADC Mode Register Interface Mode Register Understanding Configuration Flexibility CIRCUIT DESCRIPTION ANALOG INPUT Buffered Analog Input Fully Differential Inputs Single-Ended Inputs Buffer Chopping, Noise, and Input Current Running with Single Cycle = 0 Using External Buffers REFERENCE OPTIONS External Reference Internal Reference CLOCK SOURCE Internal Oscillator External Crystal External Clock DIGITAL FILTERS SINC5 + SINC1 FILTER SINC3 FILTER ENHANCED 50 Hz AND 60 Hz REJECTION FILTERS 50 Hz and 60 Hz Rejection Filter Frequency Domain Plots OPERATING MODES CONTINUOUS CONVERSION MODE CONTINUOUS READ MODE SINGLE CONVERSION MODE STANDBY AND POWER-DOWN MODES CALIBRATION MODES DIGITAL INTERFACE CHECKSUM PROTECTION CRC CALCULATION Polynomial Example of a Polynomial CRC Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) XOR Calculation Example of an XOR Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) INTEGRATED FUNCTIONS GENERAL-PURPOSE I/O EXTERNAL MULTIPLEXER CONTROL DELAY 16-BIT/24-BIT CONVERSIONS SERIAL INTERFACE RESET (DOUT_RESET) SYNCHRONIZATION Normal Synchronization Alternate Synchronization ERROR FLAGS ADC_ERROR CRC_ERROR REG_ERROR /ERROR Pin DATA_STAT IOSTRENGTH BIT GROUNDING AND LAYOUT REGISTER SUMMARY REGISTER DETAILS COMMUNICATIONS REGISTER STATUS REGISTER ADC MODE REGISTER INTERFACE MODE REGISTER REGISTER CHECK DATA REGISTER GPIO CONFIGURATION REGISTER ID REGISTER CHANNEL REGISTER 0 CHANNEL REGISTER 1 TO CHANNEL REGISTER 15 SETUP CONFIGURATION REGISTER 0 SETUP CONFIGURATION REGISTER 1 TO SETUP CONFIGURATION REGISTER 7 FILTER CONFIGURATION REGISTER 0 FILTER CONFIGURATION REGISTER 1 TO FILTER CONFIGURATION REGISTER 7 OFFSET REGISTER 0 OFFSET REGISTER 1 TO OFFSET REGISTER 7 GAIN REGISTER 0 GAIN REGISTER 1 TO GAIN REGISTER 7 OUTLINE DIMENSIONS ORDERING GUIDE NOTES
