Datasheet AD7173-8 (Analog Devices) - 8
| Manufacturer | Analog Devices |
| Description | Low Power, 8-/16-Channel, 31.25 kSPS, 24-Bit, Highly Integrated Sigma-Delta ADC |
| Pages / Page | 64 / 8 — AD7173-8. Data Sheet. TIMING CHARACTERISTICS. Table 2. Parameter. Limit … |
| Revision | B |
| File Format / Size | PDF / 1.2 Mb |
| Document Language | English |
AD7173-8. Data Sheet. TIMING CHARACTERISTICS. Table 2. Parameter. Limit at T , T. Unit. Test Conditions/Comments1, 2. MIN. MAX
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AD7173-8 Data Sheet TIMING CHARACTERISTICS
IOVDD = 2 V to 5.5 V, DGND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = IOVDD, CLOAD = 20 pF, unless otherwise noted.
Table 2. Parameter Limit at T , T Unit Test Conditions/Comments1, 2 MIN MAX
SCLK PULSE WIDTH t 25 ns min SCLK high pulse width 3 t 25 ns min SCLK low pulse width 4 READ OPERATION t 0 ns min 1 CS falling edge to DOUT/RDY active time 15 ns max IOVDD = 4.5 V to 5.5 V 40 ns max IOVDD = 2 V to 3.6 V t 3 0 ns min SCLK active edge to data valid delay4 2 12 ns max IOVDD = 4.5 V to 5.5 V 25 ns max IOVDD = 2 V to 3.6 V t 5 2.5 ns min Bus relinquish time after 5 CS inactive edge 20 ns max t 0 ns min SCLK inactive edge to 6 CS inactive edge t 10 ns min SCLK inactive edge to DOUT/ 7 RDY high/low WRITE OPERATION t 0 ns min 8 CS falling edge to SCLK active edge setup time4 t 8 ns min Data valid to SCLK edge setup time 9 t 8 ns min Data valid to SCLK edge hold time 10 t 5 ns min 11 CS rising edge to SCLK edge hold time 1 Sample tested during initial release to ensure compliance. 2 See Figure 2 and Figure 3. 3 The time required for the output to cross the VOL or VOH limits. 4 The SCLK active edge is the falling edge of SCLK. 5 RDY returns high after a read of the data register. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while RDY is high. It is important to ensure that subsequent reads do not occur close to the next output update. If the continuous read feature is enabled, the digital word can be read only once.
Timing Diagrams CS (I) t6 t1 t5 DOUT/RDY (O) MSB LSB t t7 2 t3 SCLK (I) t4
002
I = INPUT, O = OUTPUT
1773- 1 Figure 2. Read Cycle Timing Diagram
CS (I) t t 8 11 SCLK (I) t9 t10 DIN (I) MSB LSB
003
I = INPUT, O = OUTPUT
1773- 1 Figure 3. Write Cycle Timing Diagram Rev. B | Page 8 of 64 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS NOISE PERFORMANCE AND RESOLUTION GETTING STARTED POWER SUPPLIES Single Supply Operation (AVSS = DGND) Split Supply Operation (AVSS ≠ DGND) DIGITAL COMMUNICATION Accessing the ADC Register Map AD7173-8 RESET CONFIGURATION OVERVIEW Channel Configuration Channel Registers ADC Setups Setup Configuration Registers Filter Configuration Registers Offset Registers Gain Registers ADC Mode and Interface Mode Configuration ADC Mode Register Interface Mode Register Understanding Configuration Flexibility CIRCUIT DESCRIPTION ANALOG INPUT Buffered Analog Input Fully Differential Inputs Single-Ended Inputs Buffer Chopping, Noise, and Input Current Running with Single Cycle = 0 Using External Buffers REFERENCE OPTIONS External Reference Internal Reference CLOCK SOURCE Internal Oscillator External Crystal External Clock DIGITAL FILTERS SINC5 + SINC1 FILTER SINC3 FILTER ENHANCED 50 Hz AND 60 Hz REJECTION FILTERS 50 Hz and 60 Hz Rejection Filter Frequency Domain Plots OPERATING MODES CONTINUOUS CONVERSION MODE CONTINUOUS READ MODE SINGLE CONVERSION MODE STANDBY AND POWER-DOWN MODES CALIBRATION MODES DIGITAL INTERFACE CHECKSUM PROTECTION CRC CALCULATION Polynomial Example of a Polynomial CRC Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) XOR Calculation Example of an XOR Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) INTEGRATED FUNCTIONS GENERAL-PURPOSE I/O EXTERNAL MULTIPLEXER CONTROL DELAY 16-BIT/24-BIT CONVERSIONS SERIAL INTERFACE RESET (DOUT_RESET) SYNCHRONIZATION Normal Synchronization Alternate Synchronization ERROR FLAGS ADC_ERROR CRC_ERROR REG_ERROR /ERROR Pin DATA_STAT IOSTRENGTH BIT GROUNDING AND LAYOUT REGISTER SUMMARY REGISTER DETAILS COMMUNICATIONS REGISTER STATUS REGISTER ADC MODE REGISTER INTERFACE MODE REGISTER REGISTER CHECK DATA REGISTER GPIO CONFIGURATION REGISTER ID REGISTER CHANNEL REGISTER 0 CHANNEL REGISTER 1 TO CHANNEL REGISTER 15 SETUP CONFIGURATION REGISTER 0 SETUP CONFIGURATION REGISTER 1 TO SETUP CONFIGURATION REGISTER 7 FILTER CONFIGURATION REGISTER 0 FILTER CONFIGURATION REGISTER 1 TO FILTER CONFIGURATION REGISTER 7 OFFSET REGISTER 0 OFFSET REGISTER 1 TO OFFSET REGISTER 7 GAIN REGISTER 0 GAIN REGISTER 1 TO GAIN REGISTER 7 OUTLINE DIMENSIONS ORDERING GUIDE NOTES
AD7173-8 Data Sheet TIMING CHARACTERISTICS
IOVDD = 2 V to 5.5 V, DGND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = IOVDD, CLOAD = 20 pF, unless otherwise noted.
Table 2. Parameter Limit at T , T Unit Test Conditions/Comments1, 2 MIN MAX
SCLK PULSE WIDTH t 25 ns min SCLK high pulse width 3 t 25 ns min SCLK low pulse width 4 READ OPERATION t 0 ns min 1 CS falling edge to DOUT/RDY active time 15 ns max IOVDD = 4.5 V to 5.5 V 40 ns max IOVDD = 2 V to 3.6 V t 3 0 ns min SCLK active edge to data valid delay4 2 12 ns max IOVDD = 4.5 V to 5.5 V 25 ns max IOVDD = 2 V to 3.6 V t 5 2.5 ns min Bus relinquish time after 5 CS inactive edge 20 ns max t 0 ns min SCLK inactive edge to 6 CS inactive edge t 10 ns min SCLK inactive edge to DOUT/ 7 RDY high/low WRITE OPERATION t 0 ns min 8 CS falling edge to SCLK active edge setup time4 t 8 ns min Data valid to SCLK edge setup time 9 t 8 ns min Data valid to SCLK edge hold time 10 t 5 ns min 11 CS rising edge to SCLK edge hold time 1 Sample tested during initial release to ensure compliance. 2 See Figure 2 and Figure 3. 3 The time required for the output to cross the VOL or VOH limits. 4 The SCLK active edge is the falling edge of SCLK. 5 RDY returns high after a read of the data register. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while RDY is high. It is important to ensure that subsequent reads do not occur close to the next output update. If the continuous read feature is enabled, the digital word can be read only once.
Timing Diagrams CS (I) t6 t1 t5 DOUT/RDY (O) MSB LSB t t7 2 t3 SCLK (I) t4
002
I = INPUT, O = OUTPUT
1773- 1 Figure 2. Read Cycle Timing Diagram
CS (I) t t 8 11 SCLK (I) t9 t10 DIN (I) MSB LSB
003
I = INPUT, O = OUTPUT
1773- 1 Figure 3. Write Cycle Timing Diagram Rev. B | Page 8 of 64 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS NOISE PERFORMANCE AND RESOLUTION GETTING STARTED POWER SUPPLIES Single Supply Operation (AVSS = DGND) Split Supply Operation (AVSS ≠ DGND) DIGITAL COMMUNICATION Accessing the ADC Register Map AD7173-8 RESET CONFIGURATION OVERVIEW Channel Configuration Channel Registers ADC Setups Setup Configuration Registers Filter Configuration Registers Offset Registers Gain Registers ADC Mode and Interface Mode Configuration ADC Mode Register Interface Mode Register Understanding Configuration Flexibility CIRCUIT DESCRIPTION ANALOG INPUT Buffered Analog Input Fully Differential Inputs Single-Ended Inputs Buffer Chopping, Noise, and Input Current Running with Single Cycle = 0 Using External Buffers REFERENCE OPTIONS External Reference Internal Reference CLOCK SOURCE Internal Oscillator External Crystal External Clock DIGITAL FILTERS SINC5 + SINC1 FILTER SINC3 FILTER ENHANCED 50 Hz AND 60 Hz REJECTION FILTERS 50 Hz and 60 Hz Rejection Filter Frequency Domain Plots OPERATING MODES CONTINUOUS CONVERSION MODE CONTINUOUS READ MODE SINGLE CONVERSION MODE STANDBY AND POWER-DOWN MODES CALIBRATION MODES DIGITAL INTERFACE CHECKSUM PROTECTION CRC CALCULATION Polynomial Example of a Polynomial CRC Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) XOR Calculation Example of an XOR Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) INTEGRATED FUNCTIONS GENERAL-PURPOSE I/O EXTERNAL MULTIPLEXER CONTROL DELAY 16-BIT/24-BIT CONVERSIONS SERIAL INTERFACE RESET (DOUT_RESET) SYNCHRONIZATION Normal Synchronization Alternate Synchronization ERROR FLAGS ADC_ERROR CRC_ERROR REG_ERROR /ERROR Pin DATA_STAT IOSTRENGTH BIT GROUNDING AND LAYOUT REGISTER SUMMARY REGISTER DETAILS COMMUNICATIONS REGISTER STATUS REGISTER ADC MODE REGISTER INTERFACE MODE REGISTER REGISTER CHECK DATA REGISTER GPIO CONFIGURATION REGISTER ID REGISTER CHANNEL REGISTER 0 CHANNEL REGISTER 1 TO CHANNEL REGISTER 15 SETUP CONFIGURATION REGISTER 0 SETUP CONFIGURATION REGISTER 1 TO SETUP CONFIGURATION REGISTER 7 FILTER CONFIGURATION REGISTER 0 FILTER CONFIGURATION REGISTER 1 TO FILTER CONFIGURATION REGISTER 7 OFFSET REGISTER 0 OFFSET REGISTER 1 TO OFFSET REGISTER 7 GAIN REGISTER 0 GAIN REGISTER 1 TO GAIN REGISTER 7 OUTLINE DIMENSIONS ORDERING GUIDE NOTES
