Datasheet LTC7851, LTC7851-1 (Analog Devices) - 9
| Manufacturer | Analog Devices |
| Description | Quad Output, Multiphase Step-Down Voltage Mode DC/DC Controller with Accurate Current Sharing |
| Pages / Page | 38 / 9 — PIN FUNCTIONS COMP1 (Pin 1), COMP2 (Pin 9), COMP3 (Pin 13), COMP4. VCC … |
| Revision | A |
| File Format / Size | PDF / 4.2 Mb |
| Document Language | English |
PIN FUNCTIONS COMP1 (Pin 1), COMP2 (Pin 9), COMP3 (Pin 13), COMP4. VCC (Pin 11):. (Pin 20):
Model Line for this Datasheet
Text Version of Document
LTC7851/LTC7851-1
PIN FUNCTIONS COMP1 (Pin 1), COMP2 (Pin 9), COMP3 (Pin 13), COMP4 VCC (Pin 11):
Chip Supply Voltage. Bypass this pin to GND
(Pin 20):
Error Amplifier Outputs. PWM duty cycle in- with a capacitor (0.1μF to 1μF ceramic) in close proximity creases with this control voltage. The error amplifiers in to the chip. the LTC7851/LTC7851-1 are true operational amplifiers
TRACK/SS1 (Pin 57), TRACK/SS2 (Pin 40), TRACK/SS3
with low output impedance. As a result, the outputs of
(Pin 37), TRACK/SS4 (Pin 22):
Combined Soft-Start and two active error amplifiers cannot be directly connected Tracking Inputs. For soft-start operation, connecting a together! For multiphase operation, connecting the FB pin capacitor from this pin to ground will control the voltage on an error amplifier to VCC will three-state the output of ramp at the output of the power supply. An internal 2.5μA that amplifier. Multiphase operation can then be achieved current source will charge the capacitor and thereby control by connecting all of the COMP pins together and using an extra input on the reference side of the error amplifier. one channel as the master and all others as slaves. When For coincident tracking of both outputs at start-up, a re- the RUN pin is low, the respective COMP pin is actively sistor divider with values equal to those connected to the pulled down to ground. secondary VSNSP pin from the secondary output should
VSNSP1 (Pin 2), VSNSP2 (Pin 8), VSNSP3 (Pin 14),
be used to connect the secondary track input from the
VSNSP4 (Pin 19):
Differential Sense Amplifier Noninverting primary output. This pin is internally clamped to 2V, and Input. Connect this pin to the midpoint of the feedback is used to communicate over current events in a master- resistive divider between the positive and negative output slave configuration. capacitor terminals.
RUN1 (Pin 53), RUN2 (Pin 51), RUN3 (Pin 27), RUN4 (Pin VSNSN1 (Pin 3), VSNSN2 (Pin 7), VSNSN3 (Pin 15), 23):
Run Control Inputs. A voltage above 2.25V on either
VSNSN4 (Pin 18):
Differential Sense Amplifier Inverting pin turns on the IC. However, forcing a RUN pin below 2V Input. Connect this pin to sense ground at the output load. causes the IC to shut down that particular channel. There If the differential sense amplifier is not used, connect this are 1.5μA pull-up currents for these pins. pin to local ground. Float this pin when the channel is a
PWM1 (Pin 52), PWM2 (Pin 50), PWM3 (Pin 26), PWM4
slave channel.
(Pin 24):
(Top) Gate Signal Output. This signal goes to
VSNSOUT1 (Pin 4), VSNSOUT2 (Pin 6), VSNSOUT3
the PWM or top gate input of the external gate driver or
(Pin 16), VSNSOUT4 (Pin 17):
Differential Amplifier Output. integrated driver MOSFET. This is a three-state compat- Connect to the corresponding FB pin with a compensation ible output. In three-state, the voltage of this pin will be network for remote VOUT sensing. PolyPhase control is also determined by the external resistor divider. implemented in part by connecting all slave VSNSOUT pins
PGOOD1 (Pin 49), PGOOD2 (Pin 38), PGOOD3 (Pin 28),
to the master VSNSOUT output. Only the master phase’s
PGOOD4 (Pin 25):
Power Good Indicator Output for Each differential amplifier contributes information to this output. Channel. Open-drain logic out that is pulled to SGND when
SGND (Pin 5, Exposed Pad Pin 59):
Signal Ground. All either channel output exceeds a ±10% regulation window, soft-start, small-signal and compensation components after the internal 30μs power bad mask timer expires. should return to SGND. The exposed pad must be soldered
I
to PCB ground for rated thermal performance.
LIM1 (Pin 48), ILIM2 (Pin 41), ILIM3 (Pin 36), ILIM4 (Pin 29):
Current Comparator Sense Voltage Limit Selection
FB1 (Pin 58), FB2 (Pin 10), FB3 (Pin 12), FB4 (Pin 21):
Pin. Connect a resistor from this pin to SGND. This pin Error Amplifier Inverting Input. Connect to the correspond- sources 20μA when the channel is a master channel. ing VSNSOUT pin with a compensation network for remote This pin does not source current when the channel is a VOUT sensing. Connecting the FB to VCC disables the dif- slave channel. The resultant voltage sets the threshold for ferential and error amplifiers of the respective channel, overcurrent protection. For multiphase operation, all ILIM and will three-state the amplifier outputs. pins are tied together and only master channel's ILIM pin sources 20μA. Rev A For more information www.analog.com 9 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Package Description Typical Application Related Parts
PIN FUNCTIONS COMP1 (Pin 1), COMP2 (Pin 9), COMP3 (Pin 13), COMP4 VCC (Pin 11):
Chip Supply Voltage. Bypass this pin to GND
(Pin 20):
Error Amplifier Outputs. PWM duty cycle in- with a capacitor (0.1μF to 1μF ceramic) in close proximity creases with this control voltage. The error amplifiers in to the chip. the LTC7851/LTC7851-1 are true operational amplifiers
TRACK/SS1 (Pin 57), TRACK/SS2 (Pin 40), TRACK/SS3
with low output impedance. As a result, the outputs of
(Pin 37), TRACK/SS4 (Pin 22):
Combined Soft-Start and two active error amplifiers cannot be directly connected Tracking Inputs. For soft-start operation, connecting a together! For multiphase operation, connecting the FB pin capacitor from this pin to ground will control the voltage on an error amplifier to VCC will three-state the output of ramp at the output of the power supply. An internal 2.5μA that amplifier. Multiphase operation can then be achieved current source will charge the capacitor and thereby control by connecting all of the COMP pins together and using an extra input on the reference side of the error amplifier. one channel as the master and all others as slaves. When For coincident tracking of both outputs at start-up, a re- the RUN pin is low, the respective COMP pin is actively sistor divider with values equal to those connected to the pulled down to ground. secondary VSNSP pin from the secondary output should
VSNSP1 (Pin 2), VSNSP2 (Pin 8), VSNSP3 (Pin 14),
be used to connect the secondary track input from the
VSNSP4 (Pin 19):
Differential Sense Amplifier Noninverting primary output. This pin is internally clamped to 2V, and Input. Connect this pin to the midpoint of the feedback is used to communicate over current events in a master- resistive divider between the positive and negative output slave configuration. capacitor terminals.
RUN1 (Pin 53), RUN2 (Pin 51), RUN3 (Pin 27), RUN4 (Pin VSNSN1 (Pin 3), VSNSN2 (Pin 7), VSNSN3 (Pin 15), 23):
Run Control Inputs. A voltage above 2.25V on either
VSNSN4 (Pin 18):
Differential Sense Amplifier Inverting pin turns on the IC. However, forcing a RUN pin below 2V Input. Connect this pin to sense ground at the output load. causes the IC to shut down that particular channel. There If the differential sense amplifier is not used, connect this are 1.5μA pull-up currents for these pins. pin to local ground. Float this pin when the channel is a
PWM1 (Pin 52), PWM2 (Pin 50), PWM3 (Pin 26), PWM4
slave channel.
(Pin 24):
(Top) Gate Signal Output. This signal goes to
VSNSOUT1 (Pin 4), VSNSOUT2 (Pin 6), VSNSOUT3
the PWM or top gate input of the external gate driver or
(Pin 16), VSNSOUT4 (Pin 17):
Differential Amplifier Output. integrated driver MOSFET. This is a three-state compat- Connect to the corresponding FB pin with a compensation ible output. In three-state, the voltage of this pin will be network for remote VOUT sensing. PolyPhase control is also determined by the external resistor divider. implemented in part by connecting all slave VSNSOUT pins
PGOOD1 (Pin 49), PGOOD2 (Pin 38), PGOOD3 (Pin 28),
to the master VSNSOUT output. Only the master phase’s
PGOOD4 (Pin 25):
Power Good Indicator Output for Each differential amplifier contributes information to this output. Channel. Open-drain logic out that is pulled to SGND when
SGND (Pin 5, Exposed Pad Pin 59):
Signal Ground. All either channel output exceeds a ±10% regulation window, soft-start, small-signal and compensation components after the internal 30μs power bad mask timer expires. should return to SGND. The exposed pad must be soldered
I
to PCB ground for rated thermal performance.
LIM1 (Pin 48), ILIM2 (Pin 41), ILIM3 (Pin 36), ILIM4 (Pin 29):
Current Comparator Sense Voltage Limit Selection
FB1 (Pin 58), FB2 (Pin 10), FB3 (Pin 12), FB4 (Pin 21):
Pin. Connect a resistor from this pin to SGND. This pin Error Amplifier Inverting Input. Connect to the correspond- sources 20μA when the channel is a master channel. ing VSNSOUT pin with a compensation network for remote This pin does not source current when the channel is a VOUT sensing. Connecting the FB to VCC disables the dif- slave channel. The resultant voltage sets the threshold for ferential and error amplifiers of the respective channel, overcurrent protection. For multiphase operation, all ILIM and will three-state the amplifier outputs. pins are tied together and only master channel's ILIM pin sources 20μA. Rev A For more information www.analog.com 9 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Package Description Typical Application Related Parts
