Datasheet LTC7851, LTC7851-1 (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | Quad Output, Multiphase Step-Down Voltage Mode DC/DC Controller with Accurate Current Sharing |
| Pages / Page | 38 / 10 — PIN FUNCTIONS. IAVG1 (Pin 47), IAVG2 (Pin 42), IAVG3 (Pin 35), IAVG4 (Pin … |
| Revision | A |
| File Format / Size | PDF / 4.2 Mb |
| Document Language | English |
PIN FUNCTIONS. IAVG1 (Pin 47), IAVG2 (Pin 42), IAVG3 (Pin 35), IAVG4 (Pin CLKOUT (Pin 54):. 30):. CLKIN (Pin 55):
Model Line for this Datasheet
Text Version of Document
LTC7851/LTC7851-1
PIN FUNCTIONS IAVG1 (Pin 47), IAVG2 (Pin 42), IAVG3 (Pin 35), IAVG4 (Pin CLKOUT (Pin 54):
Digital Output used for Daisychaining
30):
Average Current Monitor Pin. A capacitor tied to Multiple LTC7851/LTC7851-1 ICs in Multiphase Systems. ground from the IAVG pin stores a voltage proportional to When all RUN pins are driven low, the CLKOUT pin is ac- the instantaneous average current of the master channel. tively pulled up to VCC. Signal swing is from VCC to ground. When the average current is zero, the IAVG pin voltage is
CLKIN (Pin 55):
External Clock Synchronization Input. 500mV. PolyPhase control is also implemented in part Applying an external clock between 250kHz to 2.25MHz by connecting all slave IAVG pins together to the master will cause the switching frequency to synchronize to the IAVG output. The total capacitance on the IAVG bus should clock. CLKIN is pulled high to V range from 47pF to 220pF, inclusive, with the typical value CC by a 20k internal resis- tor. The rising edge of the CLKIN input waveform will align being 100pF. Only the master phase contributes informa- with the rising edge of PWM1 in closed-loop operation. If tion to this average through an internal resistor in current CLKIN is high or floating, a resistor from the FREQ pin to sharing mode. SGND sets the switching frequency. If CLKIN is low, the
ISNS1P (Pin 46), ISNS2P (Pin 43), ISNS3P (Pin 34),
FREQ pin logic state selects an internal 600kHz or 1MHz
ISNS4P (Pin 31):
Current Sense Amplifier(+) Input. The (+) preset frequency. input to the current sense amplifier is normally connected
FREQ (Pin 56):
Frequency Set/Select Pin. This pin sources to the midpoint of the inductor’s parallel RC sense circuit 20μA current. If CLKIN is high or floating, then a resistor or to the node between the inductor and sense resistor if between this pin and SGND sets the switching frequency. If using a discrete sense resistor. CLKIN is low, the logic state of this pin selects an internal
ISNS1N (Pin 45), ISNS2N (Pin 44), ISNS3N (Pin 33),
600kHz or 1MHz preset frequency.
ISNS4N (Pin 32):
Current Sense Amplifier(–) Input. The (–) input to the current amplifier is normally connected to the respective VOUT at the inductor.
VINSNS (Pin 39):
VIN Sense Pin. Connects to the VIN power supply to provide line feedforward compensation. A change in VIN immediately modulates the input to the PWM comparator and changes the pulse width in an in- versely proportional manner, thus bypassing the feedback loop and providing excellent transient line regulation. An external lowpass filter can be added to this pin to prevent noisy signals from affecting the loop gain. Rev A 10 For more information www.analog.com Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Package Description Typical Application Related Parts
PIN FUNCTIONS IAVG1 (Pin 47), IAVG2 (Pin 42), IAVG3 (Pin 35), IAVG4 (Pin CLKOUT (Pin 54):
Digital Output used for Daisychaining
30):
Average Current Monitor Pin. A capacitor tied to Multiple LTC7851/LTC7851-1 ICs in Multiphase Systems. ground from the IAVG pin stores a voltage proportional to When all RUN pins are driven low, the CLKOUT pin is ac- the instantaneous average current of the master channel. tively pulled up to VCC. Signal swing is from VCC to ground. When the average current is zero, the IAVG pin voltage is
CLKIN (Pin 55):
External Clock Synchronization Input. 500mV. PolyPhase control is also implemented in part Applying an external clock between 250kHz to 2.25MHz by connecting all slave IAVG pins together to the master will cause the switching frequency to synchronize to the IAVG output. The total capacitance on the IAVG bus should clock. CLKIN is pulled high to V range from 47pF to 220pF, inclusive, with the typical value CC by a 20k internal resis- tor. The rising edge of the CLKIN input waveform will align being 100pF. Only the master phase contributes informa- with the rising edge of PWM1 in closed-loop operation. If tion to this average through an internal resistor in current CLKIN is high or floating, a resistor from the FREQ pin to sharing mode. SGND sets the switching frequency. If CLKIN is low, the
ISNS1P (Pin 46), ISNS2P (Pin 43), ISNS3P (Pin 34),
FREQ pin logic state selects an internal 600kHz or 1MHz
ISNS4P (Pin 31):
Current Sense Amplifier(+) Input. The (+) preset frequency. input to the current sense amplifier is normally connected
FREQ (Pin 56):
Frequency Set/Select Pin. This pin sources to the midpoint of the inductor’s parallel RC sense circuit 20μA current. If CLKIN is high or floating, then a resistor or to the node between the inductor and sense resistor if between this pin and SGND sets the switching frequency. If using a discrete sense resistor. CLKIN is low, the logic state of this pin selects an internal
ISNS1N (Pin 45), ISNS2N (Pin 44), ISNS3N (Pin 33),
600kHz or 1MHz preset frequency.
ISNS4N (Pin 32):
Current Sense Amplifier(–) Input. The (–) input to the current amplifier is normally connected to the respective VOUT at the inductor.
VINSNS (Pin 39):
VIN Sense Pin. Connects to the VIN power supply to provide line feedforward compensation. A change in VIN immediately modulates the input to the PWM comparator and changes the pulse width in an in- versely proportional manner, thus bypassing the feedback loop and providing excellent transient line regulation. An external lowpass filter can be added to this pin to prevent noisy signals from affecting the loop gain. Rev A 10 For more information www.analog.com Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Package Description Typical Application Related Parts
