Datasheet LT3579, LT3579-1 (Analog Devices) - 7
| Manufacturer | Analog Devices |
| Description | 6A Boost/Inverting DC/DC Converter with Fault Protection |
| Pages / Page | 42 / 7 — PIN FUNCTIONS (QFN/TSSOP). GATE (Pin 1/Pin 3):. SHDN (Pin 15/Pin 17):. … |
| Revision | B |
| File Format / Size | PDF / 1.1 Mb |
| Document Language | English |
PIN FUNCTIONS (QFN/TSSOP). GATE (Pin 1/Pin 3):. SHDN (Pin 15/Pin 17):. FAULT (Pin 2/Pin 4):. RT (Pin 16/Pin 18):
Model Line for this Datasheet
Text Version of Document
link to page 13 LT3579/LT3579-1
PIN FUNCTIONS (QFN/TSSOP) GATE (Pin 1/Pin 3):
PMOS Gate Drive Pin. The GATE pin cycle varies linearly with the part’s junction temperature. is a pull-down current source, and can be used to drive The CLKOUT pin signal of the LT3579-1 is 180° out of the gate of an external PMOS transistor for output short phase with the internal oscillator or SYNC pin, and the circuit protection or output disconnect. The GATE pin duty cycle is fixed at ~50%. The LT3579-1 is useful for current increases linearly with the SS pin’s voltage, with multiphase switching regulators. a maximum pull-down current of 933µA at SS voltages
SHDN (Pin 15/Pin 17):
Shutdown Pin. In conjunction exceeding 500mV. Note that if the SS voltage is greater with the UVLO (undervoltage lockout) circuit, this pin is than 500mV, and the GATE pin voltage is less than 2V, the used to enable/disable the chip and restart the soft-start GATE pin looks like a 2kΩ impedance to ground. See the sequence. Drive below 0.3V to disable the chip with very Appendix for more information. low quiescent current. Drive above 1.33V (typical) to acti-
FAULT (Pin 2/Pin 4):
Fault Indication Pin. This active low, vate the chip and restart the soft-start sequence. Do not bidirectional pin can either be pulled low (below 750mV) float this pin. by an external source, or internally by the chip to indi-
RT (Pin 16/Pin 18):
Timing Resistor Pin. Adjusts the cate a fault. When pulled low, this pin causes the power LT3579’s switching frequency. Place a resistor from this switches to turn off, the GATE pin to become high imped- pin to ground to set the frequency to a fixed free running ance, the CLKOUT pin to become disabled, and the SS level. Do not float this pin. pin to go through a charge/discharge sequence. The end/ absence of a fault is indicated when the voltage on this
SYNC (Pin 17/Pin 20):
To synchronize the switching fre- pin exceeds 1V. A pull-up resistor or some other form of quency to an outside clock, simply drive this pin with a pull-up network needs to exist on this pin to pull it above clock. The high voltage level of the clock must exceed 1V in the absence of a fault. 1.3V, and the low level must be less than 0.4V. Drive this pin to less than 0.4V to revert to the internal free running
VIN (Pin 3/Pin 5):
Input Supply Pin. Must be locally clock. See the Applications Information section for more bypassed. information.
SW1 (Pins 4 - 7/Pins 6 - 10):
Master Switch Pin. This is the
SS (Pin 18/Pin 19):
Soft-Start Pin. Place a soft-start collector of the internal master NPN power switch. SW1 capacitor here. Upon start-up, the SS pin will be charged is designed to handle a peak col ector current of 3.4A by a (nominally) 250kΩ resistor to ~2.1V. During a fault, (minimum). Minimize the metal trace area connected to the SS pin will be slowly charged up and discharged as this pin to minimize EMI. part of a timeout sequence.
GND (Pins 8, 9, Exposed Pad Pin 21/Exposed Pad Pin 21): V
Ground. Must be soldered directly to local ground plane.
C (Pin 19/Pin 2):
Error Amplifier Output Pin. Tie external com pensation network to this pin.
SW2 (Pins 10-13/Pins 11-15):
Slave Switch Pin. This is
FB (Pin 20/Pin 1):
Positive and Negative Feedback Pin. the collector of the internal slave NPN power switch. SW2 For a Boost or Inverting Converter, tie a resistor from the is designed to handle a peak col ector current of 2.6A FB pin to V (minimum). Minimize the metal trace area connected to OUT according to the following equations: this pin to minimize EMI. ⎛ V R OUT – 1.215V ⎞
CLKOUT (Pin 14/Pin 16):
Clock Output Pin. Use this pin to
FB = ⎝⎜ 83.3µA ⎠⎟ ; Boost or SEPIC Converter synchronize one or more other ICs to the LT3579. This pin ⎛ | V ⎞ oscillates at the same frequency as the internal oscillator R OUT | +9mV FB = ⎝⎜ 83.3µA of the part or as the SYNC pin. CLKOUT may also be used ⎠⎟ ; Inverting Converter as a temperature monitor since the CLKOUT pin’s duty Rev. B For more information www.analog.com 7 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram State Diagram Operation Applications Information Appendix Typical Application Package Description Typical Application Related Parts Features Applications Typical Application Description Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram State Diagram Operation Applications Information Appendix Typical Application Package Description Revision History Typical Application Related Parts
PIN FUNCTIONS (QFN/TSSOP) GATE (Pin 1/Pin 3):
PMOS Gate Drive Pin. The GATE pin cycle varies linearly with the part’s junction temperature. is a pull-down current source, and can be used to drive The CLKOUT pin signal of the LT3579-1 is 180° out of the gate of an external PMOS transistor for output short phase with the internal oscillator or SYNC pin, and the circuit protection or output disconnect. The GATE pin duty cycle is fixed at ~50%. The LT3579-1 is useful for current increases linearly with the SS pin’s voltage, with multiphase switching regulators. a maximum pull-down current of 933µA at SS voltages
SHDN (Pin 15/Pin 17):
Shutdown Pin. In conjunction exceeding 500mV. Note that if the SS voltage is greater with the UVLO (undervoltage lockout) circuit, this pin is than 500mV, and the GATE pin voltage is less than 2V, the used to enable/disable the chip and restart the soft-start GATE pin looks like a 2kΩ impedance to ground. See the sequence. Drive below 0.3V to disable the chip with very Appendix for more information. low quiescent current. Drive above 1.33V (typical) to acti-
FAULT (Pin 2/Pin 4):
Fault Indication Pin. This active low, vate the chip and restart the soft-start sequence. Do not bidirectional pin can either be pulled low (below 750mV) float this pin. by an external source, or internally by the chip to indi-
RT (Pin 16/Pin 18):
Timing Resistor Pin. Adjusts the cate a fault. When pulled low, this pin causes the power LT3579’s switching frequency. Place a resistor from this switches to turn off, the GATE pin to become high imped- pin to ground to set the frequency to a fixed free running ance, the CLKOUT pin to become disabled, and the SS level. Do not float this pin. pin to go through a charge/discharge sequence. The end/ absence of a fault is indicated when the voltage on this
SYNC (Pin 17/Pin 20):
To synchronize the switching fre- pin exceeds 1V. A pull-up resistor or some other form of quency to an outside clock, simply drive this pin with a pull-up network needs to exist on this pin to pull it above clock. The high voltage level of the clock must exceed 1V in the absence of a fault. 1.3V, and the low level must be less than 0.4V. Drive this pin to less than 0.4V to revert to the internal free running
VIN (Pin 3/Pin 5):
Input Supply Pin. Must be locally clock. See the Applications Information section for more bypassed. information.
SW1 (Pins 4 - 7/Pins 6 - 10):
Master Switch Pin. This is the
SS (Pin 18/Pin 19):
Soft-Start Pin. Place a soft-start collector of the internal master NPN power switch. SW1 capacitor here. Upon start-up, the SS pin will be charged is designed to handle a peak col ector current of 3.4A by a (nominally) 250kΩ resistor to ~2.1V. During a fault, (minimum). Minimize the metal trace area connected to the SS pin will be slowly charged up and discharged as this pin to minimize EMI. part of a timeout sequence.
GND (Pins 8, 9, Exposed Pad Pin 21/Exposed Pad Pin 21): V
Ground. Must be soldered directly to local ground plane.
C (Pin 19/Pin 2):
Error Amplifier Output Pin. Tie external com pensation network to this pin.
SW2 (Pins 10-13/Pins 11-15):
Slave Switch Pin. This is
FB (Pin 20/Pin 1):
Positive and Negative Feedback Pin. the collector of the internal slave NPN power switch. SW2 For a Boost or Inverting Converter, tie a resistor from the is designed to handle a peak col ector current of 2.6A FB pin to V (minimum). Minimize the metal trace area connected to OUT according to the following equations: this pin to minimize EMI. ⎛ V R OUT – 1.215V ⎞
CLKOUT (Pin 14/Pin 16):
Clock Output Pin. Use this pin to
FB = ⎝⎜ 83.3µA ⎠⎟ ; Boost or SEPIC Converter synchronize one or more other ICs to the LT3579. This pin ⎛ | V ⎞ oscillates at the same frequency as the internal oscillator R OUT | +9mV FB = ⎝⎜ 83.3µA of the part or as the SYNC pin. CLKOUT may also be used ⎠⎟ ; Inverting Converter as a temperature monitor since the CLKOUT pin’s duty Rev. B For more information www.analog.com 7 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram State Diagram Operation Applications Information Appendix Typical Application Package Description Typical Application Related Parts Features Applications Typical Application Description Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram State Diagram Operation Applications Information Appendix Typical Application Package Description Revision History Typical Application Related Parts
