Datasheet KSZ8842-16M, KSZ8842-32M (Microchip) - 9

ManufacturerMicrochip
DescriptionTwo-Port Ethernet Switch with Non-PCI Interface
Pages / Page132 / 9 — KSZ8842-16M/-32M. TABLE 2-1:. PIN DESCRIPTION FOR KSZ8842-16MQL/MVL …
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KSZ8842-16M/-32M. TABLE 2-1:. PIN DESCRIPTION FOR KSZ8842-16MQL/MVL (8-/16-BIT) (CONTINUED). Pin. Pin Name. Type. Description. Number

KSZ8842-16M/-32M TABLE 2-1: PIN DESCRIPTION FOR KSZ8842-16MQL/MVL (8-/16-BIT) (CONTINUED) Pin Pin Name Type Description Number

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KSZ8842-16M/-32M TABLE 2-1: PIN DESCRIPTION FOR KSZ8842-16MQL/MVL (8-/16-BIT) (CONTINUED) Pin Pin Name Type Description Number
Port 1 LED indicator 27 P1LED3 OPD See the description in pins 3, 4, and 5. EEPROM Data Out 28 EEDO OPD This pin is connected to DI input of the serial EEPROM. EEPROM Serial Clock A 4 μs (OBCR[1:0] = 11 on-chip bus speed @ 25 MHz) or 800 ns 29 EESK OPD (OBCR[1:0] = 00 on-chip bus speed @ 125 MHz) serial output clock cycle to load configuration data from the serial EEPROM. EEPROM Data In This pin is connected to DO output of the serial EEPROM when EEEN is pull-up. 30 EEDI IPD This pin can be pull-down for 8-bit bus mode, pull-up for 16-bit bus mode or don’t care for 32-bit bus mode when EEEN is pull-down (without EEPROM). Synchronous Write/Read 31 SWR IPD Write/Read signal for synchronous bus accesses. Write cycles when high and Read cycles when low. Address Enable 32 AEN IPU Address qualifier for the address decoding, active-low. Write Strobe Not 33 WRN IPD Asynchronous write strobe, active-low. 34 DGND GND Digital IO ground Address Strobe Not 35 ADSN IPD For systems that require address latching, the rising edge of ADSN indi- cates the latching moment of A15-A1 and AEN. Full-chip power-down. 36 PWRDN IPU (Low = Power down; High or floating = Normal operation). 37 AGND GND Analog ground 1.2V analog V 38 VDDA P DD input power supply from VDDCO (pin 24) through external Ferrite bead and capacitor. 39 AGND GND Analog ground 40 NC — No Connect 41 NC — No Connect 42 AGND GND Analog ground 1.2V analog V 43 VDDA P DD input power supply from VDDCO (pin 24) through external Ferrite bead and capacitor. 44 NC — No Connect 45 RXP1 I/O Port 1 physical receive (MDI) or transmit signal (+ differential) 46 RXM1 I/O Port 1 physical receive (MDI) or transmit signal (– differential) 47 AGND GND Analog ground 48 TXP1 I/O Port 1 physical transmit (MDI) or receive (MDIX) signal (+ differential) 49 TXM1 I/O Port 1 physical transmit (MDI) or receive (MDIX) signal (– differential) 50 VDDATX P 3.3V analog VDD input power supply with well decoupling capacitors. 51 VDDARX P 3.3V analog VDD input power supply with well decoupling capacitors. 52 RXM2 I/O Port 2 physical receive (MDI) or transmit (MDIX) signal (– differential) 53 RXP2 I/O Port 2 physical receive (MDI) or transmit (MDIX) signal (+ differential) 54 AGND GND Analog ground 55 TXM2 I/O Port 2 physical receive (MDI) or transmit (MDIX) signal (– differential)  2020 Microchip Technology Inc.

DS00003459A-page 9 Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Functional Overview: Physical Layer Transceiver 3.2 Functional Overview: MAC and Switch 3.3 Bus Interface Unit (BIU) 3.4 Queue Management Unit (QMU) 3.5 Advanced Switch Functions 3.6 IEEE 802.1Q VLAN Support 3.7 QoS Priority Support 3.8 Rate-Limiting Support 3.9 Loopback Support 4.0 Register Descriptions 4.1 CPU Interface I/O Registers 4.2 Register Map: MAC and PHY 4.3 Type-of-Service (TOS) Priority Control Registers 4.4 Management Information Base (MIB) Counters 4.5 Static MAC Address Table 4.6 Dynamic MAC Address Table 4.7 VLAN Table 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 Asynchronous Timing without using Address Strobe (ADSN = 0) 7.2 Asynchronous Timing using Address Strobe (ADSN) 7.3 Asynchronous Timing using DATACSN (KSZ8842-32MQL/MVL Only) 7.4 Address Latching Timing for All Modes 7.5 Synchronous Timing in Burst Write (VLBUSN = 1) 7.6 Synchronous Timing in Burst Read (VLBUSN = 1) 7.7 Synchronous Write Timing (VLBUSN = 0) 7.8 Synchronous Read Timing (VLBUSN = 0) 7.9 EEPROM Timing 7.10 Auto-Negotiation Timing 7.11 Reset Timing 8.0 Selection of Isolation Transformers 9.0 Package Outline 9.1 Package Marking Information Appendix A: Data Sheet Revision History The Microchip Website Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service
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