Datasheet KSZ8873MML (Microchip)

ManufacturerMicrochip
DescriptionIntegrated 3-Port 10/100 Managed Switch with PHY
Pages / Page91 / 1 — KSZ8873MML. Integrated 3-Port 10/100 Managed Switch. with PHY. Features. …
File Format / SizePDF / 1.3 Mb
Document Languageenglish

KSZ8873MML. Integrated 3-Port 10/100 Managed Switch. with PHY. Features. • Advanced Switch Features. • Switch Monitoring Features

Datasheet KSZ8873MML Microchip

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KSZ8873MML Integrated 3-Port 10/100 Managed Switch with PHY Features
- Full-Duplex IEEE 802.3x Flow Control (PAUSE) with Force Mode Option
• Advanced Switch Features
- IEEE 802.1q VLAN Support for Up to 16 Groups - Half-Duplex Back Pressure Flow Control (Full Range of VLAN IDs) - HP Auto MDI-X for Reliable Detection of and - VLAN ID Tag/Untag Options, Per Port Basis Correction for Straight-Through and Crossover Cables with Disable and Enable Option - IEEE 802.1p/q Tag Insertion or Removal on a Per Port Basis (Egress) - MAC MII Interface Supports both MAC Mode and PHY Mode - Programmable Rate Limiting at the Ingress and Egress on a Per Port Basis - LinkMD® TDR-Based Cable Diagnostics Permit Identification of Faulty Copper Cabling - Broadcast Storm Protection with Percent Con- trol (Global and Per Port Basis) - Comprehensive LED Indicator Support for Link, Activity, Full-/Half-Duplex, and 10/100 Speed - IEEE 802.1d Rapid Spanning Tree Protocol Support - HBM ESD Rating 3 kV - Tail Tag Mode (1 byte Added before FCS) Sup-
• Switch Monitoring Features
port at Port 3 to Inform the Processor which - Port Mirroring/Monitoring/Sniffing: Ingress and/ Ingress Port Receives the Packets or Egress Traffic to Any Port or MII - Bypass Feature that Automatically Sustains the - MIB Counters for Ful y Compliant Statistics Switch Function between Port 1 and Port 2 Gathering, 34 MIB Counters Per Port when CPU (Port 3 Interface) Goes into Sleep - Loopback Modes for Remote Diagnostic of Fail- Mode ure - Self-Address Filtering Support
• Low Power Dissipation
- Individual MAC Address for Port 1 and Port 2 - Full-Chip Software Power-Down (Register Con- - IGMP Snooping (IPv4) Support for Multicast figuration Not Saved) Packet Filtering - Full-Chip Hardware Power-Down (Register - IPv4/IPv6 QoS Support Configuration Not Saved) - MAC Filtering Function to Forward Unknown - Energy-Detect Mode Support Unicast Packets to Specified Port - Dynamic Clock Tree Shutdown Feature
• Comprehensive Configuration Register Access
- Per Port Based Software Power-Save on PHY - Serial Management Interface (SMI) to All Inter- (Idle Link Detection, Register Configuration Pre- nal Registers served) - MII Management (MIIM) Interface to PHY Reg- - Voltages: Single 3.3V Supply with Internal 1.8V isters LDO for 3.3V VDDIO - High Speed SPI and I2C Interface to All Internal - Optional 3.3V, 2.5V, and 1.8V for VDDIO Registers - Transceiver Power 3.3V for VDDA_3.3 - I/O Pins Strapping and EEPROM to Program
• Industrial Temperature Range: –40°C to +85°C
Selective Registers in Unmanaged Switch
• Available in a 64-Pin LQFP, Lead-Free Package
Mode - Control Registers Configurable on the Fly (Port-
Applications
Priority, 802.1p/d/q, AN…) • VoIP Phone
• QoS/CoS Packet Prioritization Support
• Set-Top/Game Box - Per Port, 802.1p and DiffServ-Based • Automotive Ethernet - Re-Mapping of 802.1p Priority Field Per Port • Industrial Control Basis, Four Priority Levels • IPTV POF
• Proven Integrated 3-Port 10/100 Ethernet Switch
• SOHO Residential Gateway - 3rd Generation Switch with Three MACs and • Broadband Gateway/Firewall/VPN One PHY Fully Compliant with IEEE 802.3u • Integrated DSL/Cable Modem Standard • Wireless LAN Access Point + Gateway - Non-Blocking Switch Fabric Ensures Fast • Standalone 10/100 Switch Packet Delivery by Utilizing a 1k MAC Address Lookup Table and a Store-and-Forward Archi- tecture  2018 Microchip Technology Inc.

DS00002776A-page 1 Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical Layer Transceiver 3.2 Power Management 3.3 MAC and Switch 3.4 Advanced Switch Functions 3.5 Spanning Tree Support 3.6 Rapid Spanning Tree Support 3.7 Tail Tagging Mode 3.8 IGMP Support 3.9 Port Mirroring Support 3.10 Rate Limiting Support 3.11 Unicast MAC Address Filtering 3.12 Configuration Interface 3.13 Loopback Support 4.0 Register Descriptions 4.1 MII Management (MIIM) Registers 4.2 Register Descriptions 4.3 Memory Map (8-Bit Registers) 4.4 Register Descriptions 4.5 Advanced Control Registers (Registers 96-198) 4.6 Static MAC Address Table 4.7 VLAN Table 4.8 Dynamic MAC Address Table 4.9 Management Information Base (MIB) Counters 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 EEPROM Timing 7.2 MAC Mode MII Timing 7.3 PHY Mode MII Timing 7.4 I2C Slave Mode Timing 7.5 SPI Timing 7.6 Auto-Negotiation Timing 7.7 MDC/MDIO Timing 7.8 Reset Timing 8.0 Reset Circuit 9.0 Selection of Isolation Transformers 10.0 Package Outline 10.1 Package Marking Information Appendix A: Data Sheet Revision History The Microchip Web Site Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service
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