Datasheet KSZ8873MML (Microchip) - 6
| Manufacturer | Microchip |
| Description | Integrated 3-Port 10/100 Managed Switch with PHY |
| Pages / Page | 91 / 6 — KSZ8873MML. TABLE 2-1:. SIGNALS. Type. Pin. Note. Description. Number. … |
| File Format / Size | PDF / 1.3 Mb |
| Document Language | English |
KSZ8873MML. TABLE 2-1:. SIGNALS. Type. Pin. Note. Description. Number. Name. 2-1
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KSZ8873MML TABLE 2-1: SIGNALS Type Pin Pin Note Description Number Name 2-1
1 RSTN IPU Hardware reset pin (active low) 2 VDDA_1.8 P 1.8V analog core power input from VDDCO (pin 59) 3 AGND GND Analog ground 4 NC NC Unused pin. No external connection. 5 NC NC Unused pin. No external connection. 6 VDDA_3.3 P 3.3V analog VDD 7 AGND GND Analog ground. Set physical transmit output current. 8 ISET O Pull-down this pin with an 11.8 kΩ 1% resistor to ground. 1.8 analog V 9 VDDA_1.8 P DD input power supply from VDDCO (pin 59) through external Ferrite bead and capacitor. 10 RXM2 I/O Physical receive or transmit signal (– differential) 11 RXP2 I/O Physical receive or transmit signal (+ differential) 12 AGND GND Analog ground. 13 TXM2 I/O Physical transmit or receive signal (– differential) 14 TXP2 I/O Physical transmit or receive signal (+ differential) 15 NC NC No Connection 16 PWRDN IPU Chip power down input (active low). 17 X1 I 25 MHz or 50 MHz crystal/oscillator clock connections. Pins (X1, X2) connect to a crystal. If an oscillator is used, X1 connects to a 3.3V tolerant oscillator and X2 is a no connect. 18 X2 O Note: Clock is ±50 ppm for both crystal and oscillator, the clock should be applied to X1 pin before reset voltage goes high. 19 SMTXEN3 IPU Switch MII transmit enable 20 SMTXD33 IPU Switch MII transmit data bit 3 21 SMTXD32 IPU Switch MII transmit data bit 2 22 SMTXD31 IPU Switch MII transmit data bit 1 23 SMTXD30 IPU Switch MII transmit data bit 0 24 GND GND Digital ground 3.3V, 2.5V, or 1.8V digital V 25 VDDIO P DD input power supply for IO with well decoupling capacitors. Switch MII transmit clock (MII modes only) 26 SMTXC3 I/O Output in PHY MII mode Input in MAC MII. DS00002776A-page 6
2018 Microchip Technology Inc. Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical Layer Transceiver 3.2 Power Management 3.3 MAC and Switch 3.4 Advanced Switch Functions 3.5 Spanning Tree Support 3.6 Rapid Spanning Tree Support 3.7 Tail Tagging Mode 3.8 IGMP Support 3.9 Port Mirroring Support 3.10 Rate Limiting Support 3.11 Unicast MAC Address Filtering 3.12 Configuration Interface 3.13 Loopback Support 4.0 Register Descriptions 4.1 MII Management (MIIM) Registers 4.2 Register Descriptions 4.3 Memory Map (8-Bit Registers) 4.4 Register Descriptions 4.5 Advanced Control Registers (Registers 96-198) 4.6 Static MAC Address Table 4.7 VLAN Table 4.8 Dynamic MAC Address Table 4.9 Management Information Base (MIB) Counters 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 EEPROM Timing 7.2 MAC Mode MII Timing 7.3 PHY Mode MII Timing 7.4 I2C Slave Mode Timing 7.5 SPI Timing 7.6 Auto-Negotiation Timing 7.7 MDC/MDIO Timing 7.8 Reset Timing 8.0 Reset Circuit 9.0 Selection of Isolation Transformers 10.0 Package Outline 10.1 Package Marking Information Appendix A: Data Sheet Revision History The Microchip Web Site Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service
KSZ8873MML TABLE 2-1: SIGNALS Type Pin Pin Note Description Number Name 2-1
1 RSTN IPU Hardware reset pin (active low) 2 VDDA_1.8 P 1.8V analog core power input from VDDCO (pin 59) 3 AGND GND Analog ground 4 NC NC Unused pin. No external connection. 5 NC NC Unused pin. No external connection. 6 VDDA_3.3 P 3.3V analog VDD 7 AGND GND Analog ground. Set physical transmit output current. 8 ISET O Pull-down this pin with an 11.8 kΩ 1% resistor to ground. 1.8 analog V 9 VDDA_1.8 P DD input power supply from VDDCO (pin 59) through external Ferrite bead and capacitor. 10 RXM2 I/O Physical receive or transmit signal (– differential) 11 RXP2 I/O Physical receive or transmit signal (+ differential) 12 AGND GND Analog ground. 13 TXM2 I/O Physical transmit or receive signal (– differential) 14 TXP2 I/O Physical transmit or receive signal (+ differential) 15 NC NC No Connection 16 PWRDN IPU Chip power down input (active low). 17 X1 I 25 MHz or 50 MHz crystal/oscillator clock connections. Pins (X1, X2) connect to a crystal. If an oscillator is used, X1 connects to a 3.3V tolerant oscillator and X2 is a no connect. 18 X2 O Note: Clock is ±50 ppm for both crystal and oscillator, the clock should be applied to X1 pin before reset voltage goes high. 19 SMTXEN3 IPU Switch MII transmit enable 20 SMTXD33 IPU Switch MII transmit data bit 3 21 SMTXD32 IPU Switch MII transmit data bit 2 22 SMTXD31 IPU Switch MII transmit data bit 1 23 SMTXD30 IPU Switch MII transmit data bit 0 24 GND GND Digital ground 3.3V, 2.5V, or 1.8V digital V 25 VDDIO P DD input power supply for IO with well decoupling capacitors. Switch MII transmit clock (MII modes only) 26 SMTXC3 I/O Output in PHY MII mode Input in MAC MII. DS00002776A-page 6
2018 Microchip Technology Inc. Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical Layer Transceiver 3.2 Power Management 3.3 MAC and Switch 3.4 Advanced Switch Functions 3.5 Spanning Tree Support 3.6 Rapid Spanning Tree Support 3.7 Tail Tagging Mode 3.8 IGMP Support 3.9 Port Mirroring Support 3.10 Rate Limiting Support 3.11 Unicast MAC Address Filtering 3.12 Configuration Interface 3.13 Loopback Support 4.0 Register Descriptions 4.1 MII Management (MIIM) Registers 4.2 Register Descriptions 4.3 Memory Map (8-Bit Registers) 4.4 Register Descriptions 4.5 Advanced Control Registers (Registers 96-198) 4.6 Static MAC Address Table 4.7 VLAN Table 4.8 Dynamic MAC Address Table 4.9 Management Information Base (MIB) Counters 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 EEPROM Timing 7.2 MAC Mode MII Timing 7.3 PHY Mode MII Timing 7.4 I2C Slave Mode Timing 7.5 SPI Timing 7.6 Auto-Negotiation Timing 7.7 MDC/MDIO Timing 7.8 Reset Timing 8.0 Reset Circuit 9.0 Selection of Isolation Transformers 10.0 Package Outline 10.1 Package Marking Information Appendix A: Data Sheet Revision History The Microchip Web Site Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service
