Datasheet KSZ8873MML (Microchip) - 8
| Manufacturer | Microchip |
| Description | Integrated 3-Port 10/100 Managed Switch with PHY |
| Pages / Page | 91 / 8 — KSZ8873MML. TABLE 2-1:. SIGNALS (CONTINUED). Type. Pin. Note. … |
| File Format / Size | PDF / 1.3 Mb |
| Document Language | English |
KSZ8873MML. TABLE 2-1:. SIGNALS (CONTINUED). Type. Pin. Note. Description. Number. Name. 2-1
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KSZ8873MML TABLE 2-1: SIGNALS (CONTINUED) Type Pin Pin Note Description Number Name 2-1
SPI slave mode/I2C slave mode: Clock input 41 SCL_MDC I/O I2C master mode: Clock output MIIM: Clock input SPI slave mode: serial data input I2C master/slave mode: Serial data input/output 42 SDA_MDIO IPU/O MIM: Data input/out Note: An external pull-up is needed on this pin when it is in use. 43 SCRS1 I/O Switch MII carrier sense 44 SCOL1 I/O Switch MII collision detect Switch MII receive clock. 45 SMRXC1 I/O Output in PHY MII mode Input in MAC MII mode Switch MII receive data bit 3 Strap option: MII mode selection for port 1 46 SMRXD13 IPU/O PU = PHY mode. PD = MAC mode (In MAC mode, port 1 MII has to connect to an powered active external PHY for the normal operation) Switch MII receive data bit 2 Strap option: Force the speed on port 1 (P1SPD) 47 SMRXD12 IPU/O PU = Force port 1 to 100BT PD = Force port 1 to 10BT Switch MII receive data bit 1 Strap option: Force duplex mode on port 1 (P1DPX) 48 SMRXD11 IPU/O PU = Port 1 default to full-duplex mode. PD = Port 1 set to half-duplex mode. Switch MII receive data bit 0 Strap option: Force flow control on port 1 (P1FFC) 49 SMRXD10 IPU/O PU = Always enable (force) port 1 flow control feature. PD = Disable. Switch MII receive data valid Strap option: Force the speed on port 3 (P3SPD) 50 SMRXDV1 IPD/O PU = Force port 3 to 10BT PD = Force port 3 to 100BT Switch port 1 MII transmit error in MII mode SMTXER1/ 51 IPD 0 = MII link indicator from host in MII PHY mode. MII_LINK_1 1 = No link on port 1 MII PHY mode and enable Bypass mode. 52 SMTXD13 I Switch MII transmit data bit 3 53 SMTXD12 I Switch MII transmit data bit 2 54 SMTXD11 I Switch MII transmit data bit 1 55 SMTXD10 I Switch MII transmit data bit 0 DS00002776A-page 8
2018 Microchip Technology Inc. Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical Layer Transceiver 3.2 Power Management 3.3 MAC and Switch 3.4 Advanced Switch Functions 3.5 Spanning Tree Support 3.6 Rapid Spanning Tree Support 3.7 Tail Tagging Mode 3.8 IGMP Support 3.9 Port Mirroring Support 3.10 Rate Limiting Support 3.11 Unicast MAC Address Filtering 3.12 Configuration Interface 3.13 Loopback Support 4.0 Register Descriptions 4.1 MII Management (MIIM) Registers 4.2 Register Descriptions 4.3 Memory Map (8-Bit Registers) 4.4 Register Descriptions 4.5 Advanced Control Registers (Registers 96-198) 4.6 Static MAC Address Table 4.7 VLAN Table 4.8 Dynamic MAC Address Table 4.9 Management Information Base (MIB) Counters 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 EEPROM Timing 7.2 MAC Mode MII Timing 7.3 PHY Mode MII Timing 7.4 I2C Slave Mode Timing 7.5 SPI Timing 7.6 Auto-Negotiation Timing 7.7 MDC/MDIO Timing 7.8 Reset Timing 8.0 Reset Circuit 9.0 Selection of Isolation Transformers 10.0 Package Outline 10.1 Package Marking Information Appendix A: Data Sheet Revision History The Microchip Web Site Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service
SPI slave mode/I2C slave mode: Clock input 41 SCL_MDC I/O I2C master mode: Clock output MIIM: Clock input SPI slave mode: serial data input I2C master/slave mode: Serial data input/output 42 SDA_MDIO IPU/O MIM: Data input/out Note: An external pull-up is needed on this pin when it is in use. 43 SCRS1 I/O Switch MII carrier sense 44 SCOL1 I/O Switch MII collision detect Switch MII receive clock. 45 SMRXC1 I/O Output in PHY MII mode Input in MAC MII mode Switch MII receive data bit 3 Strap option: MII mode selection for port 1 46 SMRXD13 IPU/O PU = PHY mode. PD = MAC mode (In MAC mode, port 1 MII has to connect to an powered active external PHY for the normal operation) Switch MII receive data bit 2 Strap option: Force the speed on port 1 (P1SPD) 47 SMRXD12 IPU/O PU = Force port 1 to 100BT PD = Force port 1 to 10BT Switch MII receive data bit 1 Strap option: Force duplex mode on port 1 (P1DPX) 48 SMRXD11 IPU/O PU = Port 1 default to full-duplex mode. PD = Port 1 set to half-duplex mode. Switch MII receive data bit 0 Strap option: Force flow control on port 1 (P1FFC) 49 SMRXD10 IPU/O PU = Always enable (force) port 1 flow control feature. PD = Disable. Switch MII receive data valid Strap option: Force the speed on port 3 (P3SPD) 50 SMRXDV1 IPD/O PU = Force port 3 to 10BT PD = Force port 3 to 100BT Switch port 1 MII transmit error in MII mode SMTXER1/ 51 IPD 0 = MII link indicator from host in MII PHY mode. MII_LINK_1 1 = No link on port 1 MII PHY mode and enable Bypass mode. 52 SMTXD13 I Switch MII transmit data bit 3 53 SMTXD12 I Switch MII transmit data bit 2 54 SMTXD11 I Switch MII transmit data bit 1 55 SMTXD10 I Switch MII transmit data bit 0 DS00002776A-page 8
2018 Microchip Technology Inc. Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical Layer Transceiver 3.2 Power Management 3.3 MAC and Switch 3.4 Advanced Switch Functions 3.5 Spanning Tree Support 3.6 Rapid Spanning Tree Support 3.7 Tail Tagging Mode 3.8 IGMP Support 3.9 Port Mirroring Support 3.10 Rate Limiting Support 3.11 Unicast MAC Address Filtering 3.12 Configuration Interface 3.13 Loopback Support 4.0 Register Descriptions 4.1 MII Management (MIIM) Registers 4.2 Register Descriptions 4.3 Memory Map (8-Bit Registers) 4.4 Register Descriptions 4.5 Advanced Control Registers (Registers 96-198) 4.6 Static MAC Address Table 4.7 VLAN Table 4.8 Dynamic MAC Address Table 4.9 Management Information Base (MIB) Counters 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 EEPROM Timing 7.2 MAC Mode MII Timing 7.3 PHY Mode MII Timing 7.4 I2C Slave Mode Timing 7.5 SPI Timing 7.6 Auto-Negotiation Timing 7.7 MDC/MDIO Timing 7.8 Reset Timing 8.0 Reset Circuit 9.0 Selection of Isolation Transformers 10.0 Package Outline 10.1 Package Marking Information Appendix A: Data Sheet Revision History The Microchip Web Site Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service
