Datasheet KSZ8895MQX, KSZ8895RQX KSZ8895FQX, KSZ8895MLX (Microchip) - 99
| Manufacturer | Microchip |
| Description | Integrated 5-Port 10/100 Managed Ethernet Switch with MII/RMII Interface |
| Pages / Page | 109 / 99 — KSZ8895MQX/RQX/FQX/MLX. 8.0. RESET CIRCUIT. FIGURE 8-1:. RECOMMENDED … |
| File Format / Size | PDF / 2.8 Mb |
| Document Language | English |
KSZ8895MQX/RQX/FQX/MLX. 8.0. RESET CIRCUIT. FIGURE 8-1:. RECOMMENDED RESET CIRCUIT. VDDIO. D1: 1N4148. KSZ8895. 5Nȍ. RST#. C 10μF
Model Line for this Datasheet
- KSZ8895FQXC KSZ8895FQXC-TR KSZ8895FQXCA KSZ8895FQXI KSZ8895FQXI-TR KSZ8895FQXIA KSZ8895ML KSZ8895MLUB KSZ8895MLUB-TR KSZ8895MLXC KSZ8895MLXC-TR KSZ8895MLXI KSZ8895MLXI-TR KSZ8895MQ KSZ8895MQI KSZ8895MQXC KSZ8895MQXC-TR KSZ8895MQXCA KSZ8895MQXI KSZ8895MQXI-TR KSZ8895MQXIA KSZ8895RQI KSZ8895RQXC KSZ8895RQXC-TR KSZ8895RQXCA KSZ8895RQXCA-TR KSZ8895RQXI KSZ8895RQXI-TR KSZ8895RQXIA SPNY801156 SPNY801159 SPNY801159-TR SPNY801160 SPNY801160-TR SPNY801171 SPNY801172 SPNY801172-TR SPNZ801156 SPNZ801159 SPNZ801159-TR SPNZ801160 SPNZ801160-TR SPNZ801161 SPNZ801171 SPNZ801172
Text Version of Document
link to page 99 link to page 99
KSZ8895MQX/RQX/FQX/MLX 8.0 RESET CIRCUIT
A discreet reset circuit, as shown in Figure 8-1, is recommended for the power-up reset circuit.
FIGURE 8-1: RECOMMENDED RESET CIRCUIT VDDIO D1: 1N4148 KSZ8895 D1 5Nȍ RST# C 10μF
Figure 8-2 shows a reset circuit recommended for applications where reset is driven by another device (for example, the CPU or an FPGA). The reset out RST_OUT_n from CPU/FPGA provides the warm reset after power up reset. D2 is required if using different VDDIO voltage between switch and CPU/FPGA. Diode D2 should be selected to provide maximum 0.3V VF (Forward Voltage), for example, VISHAY BAT54, MSS1P2L. Alternatively, a level shifter device can also be used. D2 is not required if switch and CPU/FPGA use same VDDIO voltage.
FIGURE 8-2: RECOMMENDED RESET CIRCUIT FOR CPU/FPGA RESET OUTPUT VDDIO 5Nȍ KSZ8895 D1 CPU/FPGA RST# RST_OUT_n D2 C 10μF D1: 1N4148
2016 - 2019 Microchip Technology Inc. DS00002246B-page 99 Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical Layer Transceiver 3.2 Power 3.3 Power Management 3.4 Switch Core 3.5 Advanced Functionality 3.6 MII Management (MIIM) Interface 3.7 Serial Management Interface (SMI) 4.0 Register Descriptions 4.1 Global Registers 4.2 Port Registers 4.3 Advanced Control Registers 4.4 Static MAC Address Table 4.5 VLAN Table 4.6 Dynamic MAC Address Table 4.7 Management Information Base (MIB) Counters 4.8 MIIM Registers 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings*** 6.0 Electrical Characteristics 7.0 Timing Diagrams 7.1 EEPROM Timing 7.2 SNI Timing 7.3 MII Timing 7.4 RMII Timing 7.5 SPI Timing 7.6 Auto-Negotiation Timing 7.7 MDC/MDIO Timing 7.8 Reset Timing 8.0 Reset Circuit 9.0 Selection of Isolation Transformer, (Note 9-1) 10.0 Package Outline Appendix A: Data Sheet Revision History The Microchip Website Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service
KSZ8895MQX/RQX/FQX/MLX 8.0 RESET CIRCUIT
A discreet reset circuit, as shown in Figure 8-1, is recommended for the power-up reset circuit.
FIGURE 8-1: RECOMMENDED RESET CIRCUIT VDDIO D1: 1N4148 KSZ8895 D1 5Nȍ RST# C 10μF
Figure 8-2 shows a reset circuit recommended for applications where reset is driven by another device (for example, the CPU or an FPGA). The reset out RST_OUT_n from CPU/FPGA provides the warm reset after power up reset. D2 is required if using different VDDIO voltage between switch and CPU/FPGA. Diode D2 should be selected to provide maximum 0.3V VF (Forward Voltage), for example, VISHAY BAT54, MSS1P2L. Alternatively, a level shifter device can also be used. D2 is not required if switch and CPU/FPGA use same VDDIO voltage.
FIGURE 8-2: RECOMMENDED RESET CIRCUIT FOR CPU/FPGA RESET OUTPUT VDDIO 5Nȍ KSZ8895 D1 CPU/FPGA RST# RST_OUT_n D2 C 10μF D1: 1N4148
2016 - 2019 Microchip Technology Inc. DS00002246B-page 99 Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical Layer Transceiver 3.2 Power 3.3 Power Management 3.4 Switch Core 3.5 Advanced Functionality 3.6 MII Management (MIIM) Interface 3.7 Serial Management Interface (SMI) 4.0 Register Descriptions 4.1 Global Registers 4.2 Port Registers 4.3 Advanced Control Registers 4.4 Static MAC Address Table 4.5 VLAN Table 4.6 Dynamic MAC Address Table 4.7 Management Information Base (MIB) Counters 4.8 MIIM Registers 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings*** 6.0 Electrical Characteristics 7.0 Timing Diagrams 7.1 EEPROM Timing 7.2 SNI Timing 7.3 MII Timing 7.4 RMII Timing 7.5 SPI Timing 7.6 Auto-Negotiation Timing 7.7 MDC/MDIO Timing 7.8 Reset Timing 8.0 Reset Circuit 9.0 Selection of Isolation Transformer, (Note 9-1) 10.0 Package Outline Appendix A: Data Sheet Revision History The Microchip Website Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service
