Datasheet SLG46811 (Dialog Semiconductor) - 53

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SLG46811 GreenPAK Programmable Mixed-Signal Matrix Preliminary 8 Multi-Function Macrocells
The SLG46811 has 6 Multi-Function macrocells that can serve more than one logic or timing function. In each case, they can serve as a LUT, DFF with flexible settings, or as CNT/DLY with multiple modes such as One Shot, Frequency Detect, Edge Detect, and others. Also, the macrocell is capable to combine those functions: LUT/DFF connected to CNT/DLY or CNT/DLY connected to LUT/DFF, see Figure 34. See the list below for the functions that can be implemented in these macrocells: Five macrocells that can serve as 3-bit LUTs/D Flip-Flops and as 8-Bit Counter/Delays One macrocell that can serve as a 3-bit LUT/D Flip-Flop and as 8-Bit Counter/Delay/FSM To Connection Matrix To Connection Matrix From Connection From Connection To Connection Matrix LUT To Connection LUT Matrix Matrix Matrix or CNT/DLY CNT/DLY or DFF DFF
Figure 34: Possible Connections Inside Multi-Function Macrocell
Inputs/Outputs for the 6 Multi-Function function macrocells are configured from the connection matrix with specific logic functions being defined by the state of NVM bits. When used as a LUT to implement combinatorial logic functions, the outputs of the LUTs can be configured to any user defined function, including the following standard digital logic devices (AND, NAND, OR, NOR, XOR, XNOR).
8.1 3-BIT LUT OR DFF/LATCH WITH 8-BIT COUNTER/DELAY MACROCELLS
There are five macrocells that can serve as 3-bit LUTs/D Flip-Flops and as 8-Bit Counter/Delays. When used to implement LUT functions, the 3-bit LUTs each take in three input signals from the connection matrix and produce a single output, which goes back into the connection matrix or can be connected to CNT/DLY's input. When used to implement D Flip-Flop function, the three input signals from the connection matrix go to the data (D), clock (CLK), and Set/Reset (nRST/nSET) inputs of the Flip-Flop, with the output going back to the connection matrix or to the CNT/DLY's input. When used to implement Counter/Delays, each macrocell has a dedicated matrix input connection. For flexibility, each of these macrocells has a large selection of internal and external clock sources, as well as the option to chain from the output of the previous (N-1) CNT/DLY macrocell, to implement longer count/delay circuits. These macrocells can also operate in a One-Shot mode, which will generate an output pulse of user-defined width. They can also operate in a Frequency Detection or Edge Detection mode. Counter/Delay macrocell has an initial value, which define its initial value after GPAK is powered up. It is possible to select initial Low or initial High, as well as initial value defined by a Delay In signal. For example, in case initial LOW option is used, the rising edge delay will start operation. For timing diagrams refer to sections 7.1 and 8.2.
Note:
After two DFF – counters initialize with counter data = 0 after POR. Initial state = 1 – counters initialize with counter data = 0 after POR. Initial state = 0 And After two DFF is bypass – counters initialize with counter data after POR.
Datasheet Revision 2.2 3-Feb-2021
CFR0011-120-00 53 of 168 © 2021 Dialog Semiconductor Document Outline General Description Key Features Applications 1 Block Diagram 2 Pinout 2.1 Pin Configuration - STQFN- 12 3 Characteristics 3.1 Absolute Maximum Ratings 3.2 Electrostatic Discharge Ratings 3.3 Recommended Operating Conditions 3.4 Electrical Characteristics 3.5 I2C Pins Electrical Characteristics 3.6 Macrocells Current Consumption 3.7 Timing Characteristics 3.8 Counter/Delay Characteristics 3.9 Oscillator Characteristics 3.9.1 OSC Power-On Delay 3.10 MS ACMP Characteristics 3.11 Analog Temperature Sensor Characteristics 4 User Programmability 5 IO Pins 5.1 GPIO Pins 5.2 GPI Pins 5.3 Pull-Up/Down Resistors 5.4 Fast Pull-up/down during Power-up 5.5 GPI Structure 5.5.1 GPI Structure (for GPI) 5.6 GPIO with I2C Mode IO Structure 5.6.1 GPIO with I2C Mode Structure (for GPIO0 and GPIO1) 5.7 Matrix OE IO Structure 5.7.1 Matrix OE IO Structure (for GPIO2, GPIO3, GPIO7, GPIO8) 5.8 Register OE IO Structure 5.8.1 Register OE IO Structure (for GPIO4, GPIO5, GPIO6) 5.9 IO Typical Performance 6 Connection Matrix 6.1 Matrix Input Table 6.2 Matrix Output Table 6.3 Connection Matrix Virtual Inputs 6.4 Connection Matrix Virtual Outputs 7 Combination Function Macrocells 7.1 2-Bit LUT or D Flip-Flop Macrocells 7.1.1 2-Bit LUT or D Flip-Flop Macrocell Used as 2-Bit LUT 7.2 2-bit LUT or Programmable Pattern Generator 7.3 3-Bit LUT or D Flip-Flop with Set/Reset Macrocells Or Shift Register Macrocells 7.3.1 3-Bit LUT or D Flip-Flop Macrocells Used as 3-Bit LUTs 7.4 3-Bit LUT or D Flip-Flop with Set/Reset Macrocells 7.5 4-Bit LUT or D Flip-Flop with Set/Reset Macrocell 7.5.1 4-Bit LUT Macrocell Used as 4-Bit LUT 8 Multi-Function Macrocells 8.1 3-Bit LUT or DFF/Latch with 8-Bit Counter/Delay Macrocells 8.1.1 3-Bit LUT or 8-Bit CNT/DLY Block Diagrams 8.1.2 3-Bit LUT or CNT/DLYs Used as 3-Bit LUTs 8.2 CNT/DLY Timing Diagrams 8.2.1 Delay Mode CNT/DLY0 to CNT/DLY5 8.2.2 Count Mode (Count Data: 3), Counter Reset (Rising Edge Detect) CNT/DLY0 to CNT/DLY5 8.2.3 One-Shot Mode CNT/DLY0 to CNT/DLY5 8.2.4 Frequency Detection Mode CNT/DLY0 to CNT/DLY5 8.2.5 Edge Detection Mode CNT/DLY1 to CNT/DLY5 8.2.6 Delayed Edge Detection Mode CNT/DLY0 to CNT/DLY5 8.2.7 Difference in Counter Value for Counter, Delay, One-Shot, and Frequency Detect Modes 8.3 FSM Timing Diagrams 9 Multichannel Sampling Analog Comparator 9.1 Multichannel Sampling ACMP Block Diagram 9.2 MS ACMP Timing Diagrams 9.3 ACMP Typical Performance 10 Programmable Delay/Edge Detector 10.1 Programmable Delay Timing Diagram - Edge Detector OUTPUT 11 Additional Logic Function. Deglitch Filter 12 Voltage Reference 12.1 Voltage Reference Overview 12.2 Vref Selection Table 13 Clocking 13.1 OSC General description 13.2 Oscillator0 (2.048 kHz/10 kHz) 13.3 Oscillator1 (25 MHz) 13.4 CNT/DLY Clock Scheme 13.5 External Clocking 13.5.1 GPI Source for Oscillator0 (2.048kHz/10 kHz) 13.5.2 GPIO Source for Oscillator1 (25 MHz) 13.6 Oscillators Power-On Delay 13.7 Oscillators Accuracy 14 Power-On Reset 14.1 General Operation 14.2 POR Sequence 14.3 Macrocells Output States During POR Sequence 14.3.1 Initialization 14.3.2 Power-Down 15 I2C Serial Communications Macrocell 15.1 I2C Serial Communications Macrocell Overview 15.2 I2C Serial Communications Device Addressing 15.3 I2C Serial General Timing 15.4 I2C Serial Communications Commands 15.4.1 Byte Write Command 15.4.2 Sequential Write Command 15.4.3 Current Address Read Command 15.4.4 Random Read Command 15.4.5 Sequential Read Command 15.4.6 I2C Serial Reset Command 15.5 I2C Serial Command Register Map 15.6 I2C Additional Options 15.6.1 I2C Byte Write Bit Masking 16 Extended Pattern Generator 17 Analog Temperature Sensor 18 Register Definitions 18.1 Register Map 19 Package Top Marking Definitions 19.1 STQFN 12L 1.6 mm x 1.6 mm 0.4P FC, before February 1, 2021 19.2 STQFN 12L 1.6 mm x 1.6 mm 0.4P FC, after February 1, 2021 20 Package Information 20.1 Package outlines FOR STQFN 12L 1.6 mm x 1.6 mm x 0.55 mm 0.4P FC Package 20.2 Moisture Sensitivity Level 20.3 Soldering Information 21 Ordering Information 21.1 Tape and Reel Specifications 21.2 Carrier Tape Drawing and Dimensions 22 Layout Guidelines 22.1 STQFN 12L 1.6 mm x 1.6 mm x 0.55 mm 0.4P FC Package Glossary Revision History