Datasheet MAX9075, MAX9077 (Maxim) - 7
| Manufacturer | Maxim |
| Description | Low-Cost, Ultra-Small, 3µA Single-Supply Comparators |
| Pages / Page | 9 / 7 — MAX9075/MAX9077. Low-Cost, Ultra-Small, 3µA. Single-Supply Comparators. … |
| File Format / Size | PDF / 141 Kb |
| Document Language | English |
MAX9075/MAX9077. Low-Cost, Ultra-Small, 3µA. Single-Supply Comparators. Pin Configurations (continued)
Model Line for this Datasheet
Text Version of Document
MAX9075/MAX9077 Low-Cost, Ultra-Small, 3µA Single-Supply Comparators
4) Choose the threshold voltage for VIN rising (VTHR). In this example, choose VTHR = 3V. VCC 5) Calculate R2 as follows: R3 R2 = 1/{[VTHR/(VREF R1)] - 1/R1 - 1/R3} = R1 1/{[3 / (1.2 100kΩ)] - 1/100kΩ - 1/10MΩ} = 67.114kΩ VIN A 1% preferred value is 64.9kΩ. VCC OUT R2 6) Verify the threshold voltages with these formulas: GND V MAX9075 IN rising: VREF MAX9077 VTHR = VREF R1 (1/R1 + 1/R2 + 1/R3) VIN falling: VTHF = VTHR - (R1 VCC)/R3 Figure 1. Adding Hysteresis 7) Check the error due to input bias current (5nA). If the error is too large, reduce R3 and recalculate.
Pin Configurations (continued)
VTH = IB (R1 R2 R3)/(R1 + R2 + R3) = 0.2mV
Board Layout and Bypassing
TOP VIEW Use 10nF power-supply bypass capacitors. Use 100nF bypass capacitors when supply impedance is high, when supply leads are long, or when excessive noise is
+
expected on the supply lines. Minimize signal trace OUTA 1 8 VCC lengths to reduce stray capacitance. Minimize the GND 2 MAX9077 7 OUTB capacitive coupling between IN- and OUT. For slow- moving input signals (rise time > 1ms) use a 1nF INA- 3 6 INB- capacitor between IN+ and IN-. INA+ 4 5 INB+
Chip Information
PROCESS: BiCMOS
SOT23-8 +
OUTA 1 8 VCC INA- 2 7 OUTB MAX9077 INA+ 3 6 INB- GND 4 5 INB+ µ
MAX/SO
Maxim Integrated 7
4) Choose the threshold voltage for VIN rising (VTHR). In this example, choose VTHR = 3V. VCC 5) Calculate R2 as follows: R3 R2 = 1/{[VTHR/(VREF R1)] - 1/R1 - 1/R3} = R1 1/{[3 / (1.2 100kΩ)] - 1/100kΩ - 1/10MΩ} = 67.114kΩ VIN A 1% preferred value is 64.9kΩ. VCC OUT R2 6) Verify the threshold voltages with these formulas: GND V MAX9075 IN rising: VREF MAX9077 VTHR = VREF R1 (1/R1 + 1/R2 + 1/R3) VIN falling: VTHF = VTHR - (R1 VCC)/R3 Figure 1. Adding Hysteresis 7) Check the error due to input bias current (5nA). If the error is too large, reduce R3 and recalculate.
Pin Configurations (continued)
VTH = IB (R1 R2 R3)/(R1 + R2 + R3) = 0.2mV
Board Layout and Bypassing
TOP VIEW Use 10nF power-supply bypass capacitors. Use 100nF bypass capacitors when supply impedance is high, when supply leads are long, or when excessive noise is
+
expected on the supply lines. Minimize signal trace OUTA 1 8 VCC lengths to reduce stray capacitance. Minimize the GND 2 MAX9077 7 OUTB capacitive coupling between IN- and OUT. For slow- moving input signals (rise time > 1ms) use a 1nF INA- 3 6 INB- capacitor between IN+ and IN-. INA+ 4 5 INB+
Chip Information
PROCESS: BiCMOS
SOT23-8 +
OUTA 1 8 VCC INA- 2 7 OUTB MAX9077 INA+ 3 6 INB- GND 4 5 INB+ µ
MAX/SO
Maxim Integrated 7
