Datasheet TMUX1204 (Texas Instruments) - 3

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TMUX1204 www.ti.com
SCDS393A – APRIL 2019 – REVISED OCTOBER 2019
5 Pin Configuration and Functions DGS Package 10-Pin VSSOP DQA Package Top View 10-Pin USON Top View
A0 1 10 A1 A0 1 10 A1 S1 2 9 S2 S1 2 9 S2 GND 3 8 D GND 3 8 D S3 4 7 S4 S3 4 7 S4 EN 5 6 VDD EN 5 6 VDD Not to scale Not to scale
Pin Functions PIN TYPE(1) DESCRIPTION(2) NAME DGS, DQA
A0 1 I Address line 0. Controls the switch configuration as shown in Table 1. S1 2 I/O Source pin 1. Can be an input or output. GND 3 P Ground (0 V) reference S3 4 I/O Source pin 3. Can be an input or output. Active high logic enable. When this pin is low, all switches are turned off. When this pin is high, the EN 5 I A[1:0] logic inputs determine which switch is turned on. Positive power supply. This pin is the most positive power-supply potential. For reliable operation, VDD 6 P connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and GND. S4 7 I/O Source pin 4. Can be an input or output. D 8 I/O Drain pin. Can be an input or output. S2 9 I/O Source pin 2. Can be an input or output. A1 10 I Address line 1. Controls the switch configuration as shown in Table 1. (1) I = input, O = output, I/O = input and output, P = power (2) For unused pins, refer to the Device Functional Modes Copyright © 2019, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: TMUX1204 Document Outline 1 Features 2 Applications 3 Description Table of Contents 4 Revision History 5 Pin Configuration and Functions 6 Specifications 6.1 Absolute Maximum Ratings 6.2 ESD Ratings 6.3 Recommended Operating Conditions 6.4 Thermal Information 6.5 Electrical Characteristics (VDD = 5 V ±10 %) 6.6 Electrical Characteristics (VDD = 3.3 V ±10 %) 6.7 Electrical Characteristics (VDD = 1.8 V ±10 %) 6.8 Electrical Characteristics (VDD = 1.2 V ±10 %) 6.9 Typical Characteristics 7 Parameter Measurement Information 7.1 On-Resistance 7.2 Off-Leakage Current 7.3 On-Leakage Current 7.4 Transition Time 7.5 Break-Before-Make 7.6 tON(EN) and tOFF(EN) 7.7 Charge Injection 7.8 Off Isolation 7.9 Crosstalk 7.10 Bandwidth 8 Detailed Description 8.1 Functional Block Diagram 8.2 Feature Description 8.2.1 Bidirectional Operation 8.2.2 Rail to Rail Operation 8.2.3 1.8 V Logic Compatible Inputs 8.2.4 Fail-Safe Logic 8.3 Device Functional Modes 8.4 Truth Tables 9 Application and Implementation 9.1 Application Information 9.2 Typical Application 9.3 Design Requirements 9.4 Detailed Design Procedure 9.5 Application Curve 10 Power Supply Recommendations 11 Layout 11.1 Layout Guidelines 11.1.1 Layout Information 11.2 Layout Example 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 Related Documentation 12.2 Receiving Notification of Documentation Updates 12.3 Community Resources 12.4 Trademarks 12.5 Electrostatic Discharge Caution 12.6 Glossary 13 Mechanical, Packaging, and Orderable Information