Datasheet SR6P3EC4 (STMicroelectronics) - 3
| Manufacturer | STMicroelectronics |
| Description | 32-bit Arm Cortex R52+ automotive integration MCU 4 Cortex R52+ cores, 19.5 MB xMemory, 1.8 MB RAM, with embedded virtualization, safety, and security in FPBGA292 package |
| Pages / Page | 10 / 3 — SR6P3EC4 SR6P3EC6. Introduction. 1.1. Document overview. 1.2. … |
| File Format / Size | PDF / 572 Kb |
| Document Language | English |
SR6P3EC4 SR6P3EC6. Introduction. 1.1. Document overview. 1.2. Description. Table 1. SR6P3EC4 and SR6P3EC6 overview. Feature
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Text Version of Document
SR6P3EC4 SR6P3EC6 Introduction 1 Introduction 1.1 Document overview
This document provides a summary of the target specification and features of the SR6P3EC4 and SR6P3EC6 devices. For detailed information, refer to the device datasheet and reference manual. The SR6P3EC4 and SR6P3EC6 devices are based on Arm® cores. For information on the Arm®-Cortex®‑R52 and Arm® Cortex®‑M4 cores, refer to the technical reference manuals, available from the www.arm.com website. Note: The Arm word and logo are trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere. All rights reserved. Arm and Cortex are registered trademarks of Arm Limited (or its subsidiaries or affiliates) in the US and/or elsewhere.
1.2 Description
Stellar integration MCUs are designed to meet the requirements of domain controllers and ECUs with high integration, as required in the architectures of connected, updatable, automated, and electrified cars. They have superior real-time and safe performance (with the highest ASIL-D capability). Bringing hardware-based virtualization technology to MCUs, they ease the development and integration of multiple-source software on the same hardware while maximizing the resulting software performance. They offer high-efficiency OTA reprogramming capability with fast new image download and activation. They also provide high-speed security cryptographic services, for instance for network authentication.
Table 1. SR6P3EC4 and SR6P3EC6 overview Feature SR6P3EC4 and SR6P3EC6
4 cores (+2 checkers), Cortex®‑R52+ cores (+ checker cores) configurable as 3 cores (+3 checkers) Neon™ (with SIMD, dual precision floating point) No Cache (instruction/data) per core in Kbyte 16/8 Core memory protection unit (regions), Hypervisor (EL2) 24 several additional protection mechanisms in the architecture, for example: NOC firewalls OS (EL1) 24 Up to 19.5 MB xMemory (depending on the Overall including HSM in Mbytes ordered part number) Code NVM Up to 19 MB xMemory (depending on the Cluster code NVM in Mbytes ordered part number) HSM code NVM in Kbytes 512 Data NVM in Kbytes 384 RAM in Kbytes 1792 Hardware security module (HSM) - 2nd generation Yes AES-Light (cryptographic services) 2 Multipurpose accelerator in lockstep (DSPH) 1 Arm® Cortex®‑M4 Multi-purpose accelerator in lockstep (DME) No eDMA engines (number of channels, more Engine 4 channels through muxes/channel) Channel 4× 32 LIN and UART (LINFlexD) 8 CAN_FD 10 CAN_XL 2 (2 common with above CAN_FD channels)
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Rev 4 page 3/10
Document Outline SR6P3EC4 SR6P3EC6 Features 1 Introduction 1.1 Document overview 1.2 Description 1.3 Block diagram 2 Ordering information Revision history Glossary ADC AEC AES ASIL ATOM CAN CAN FD® CAN XL® CPU CRC DCF DMA DSP eDMA EMC EVITA FCCU FPBGA FPU GB GPIO GTM HSM I/O I2C IEC IEEE IPv4 IPv6 ISO JTAG KB LIN LVDS M_TTCAN MB MCAN MCS MCU MII NoC NPU NVM OA3p OS OSR OTA PHY PLL PSI5 RAM RGMII RMII SAR SDADC SENT SIMD SIPI SPI SPIQ SRAM SRC ST SWD TIM TIO TOM UART VLAN xMemory XS_CAN
This document provides a summary of the target specification and features of the SR6P3EC4 and SR6P3EC6 devices. For detailed information, refer to the device datasheet and reference manual. The SR6P3EC4 and SR6P3EC6 devices are based on Arm® cores. For information on the Arm®-Cortex®‑R52 and Arm® Cortex®‑M4 cores, refer to the technical reference manuals, available from the www.arm.com website. Note: The Arm word and logo are trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere. All rights reserved. Arm and Cortex are registered trademarks of Arm Limited (or its subsidiaries or affiliates) in the US and/or elsewhere.
1.2 Description
Stellar integration MCUs are designed to meet the requirements of domain controllers and ECUs with high integration, as required in the architectures of connected, updatable, automated, and electrified cars. They have superior real-time and safe performance (with the highest ASIL-D capability). Bringing hardware-based virtualization technology to MCUs, they ease the development and integration of multiple-source software on the same hardware while maximizing the resulting software performance. They offer high-efficiency OTA reprogramming capability with fast new image download and activation. They also provide high-speed security cryptographic services, for instance for network authentication.
Table 1. SR6P3EC4 and SR6P3EC6 overview Feature SR6P3EC4 and SR6P3EC6
4 cores (+2 checkers), Cortex®‑R52+ cores (+ checker cores) configurable as 3 cores (+3 checkers) Neon™ (with SIMD, dual precision floating point) No Cache (instruction/data) per core in Kbyte 16/8 Core memory protection unit (regions), Hypervisor (EL2) 24 several additional protection mechanisms in the architecture, for example: NOC firewalls OS (EL1) 24 Up to 19.5 MB xMemory (depending on the Overall including HSM in Mbytes ordered part number) Code NVM Up to 19 MB xMemory (depending on the Cluster code NVM in Mbytes ordered part number) HSM code NVM in Kbytes 512 Data NVM in Kbytes 384 RAM in Kbytes 1792 Hardware security module (HSM) - 2nd generation Yes AES-Light (cryptographic services) 2 Multipurpose accelerator in lockstep (DSPH) 1 Arm® Cortex®‑M4 Multi-purpose accelerator in lockstep (DME) No eDMA engines (number of channels, more Engine 4 channels through muxes/channel) Channel 4× 32 LIN and UART (LINFlexD) 8 CAN_FD 10 CAN_XL 2 (2 common with above CAN_FD channels)
DB5468
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Rev 4 page 3/10
Document Outline SR6P3EC4 SR6P3EC6 Features 1 Introduction 1.1 Document overview 1.2 Description 1.3 Block diagram 2 Ordering information Revision history Glossary ADC AEC AES ASIL ATOM CAN CAN FD® CAN XL® CPU CRC DCF DMA DSP eDMA EMC EVITA FCCU FPBGA FPU GB GPIO GTM HSM I/O I2C IEC IEEE IPv4 IPv6 ISO JTAG KB LIN LVDS M_TTCAN MB MCAN MCS MCU MII NoC NPU NVM OA3p OS OSR OTA PHY PLL PSI5 RAM RGMII RMII SAR SDADC SENT SIMD SIPI SPI SPIQ SRAM SRC ST SWD TIM TIO TOM UART VLAN xMemory XS_CAN