Datasheet EPC23111 (Efficient Power Conversion) - 2
| Manufacturer | Efficient Power Conversion |
| Description | 100V, 20 A ePower Stage IC |
| Pages / Page | 17 / 2 — eGaN® IC DATASHEET. Figure 2: EPC23111 Quad Flat No-Lead (QFN). Package … |
| File Format / Size | PDF / 1.9 Mb |
| Document Language | English |
eGaN® IC DATASHEET. Figure 2: EPC23111 Quad Flat No-Lead (QFN). Package (Transparent Top View). EPC23111 Pinout Description
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eGaN® IC DATASHEET
EPC23111
Figure 2: EPC23111 Quad Flat No-Lead (QFN) Package (Transparent Top View) EPC23111 Pinout Description Pin Pin Pin Name Type Description 1
PWM L Single pin PWM logic input referenced to AGND. Internal pull-down resistor is connected between PWM and AGND. SW follows PWM pin when EN is high
10 9 8 2
EN L Enable logic input referenced to AGND. Internal pull-down resistor is connected between EN and AGND. Both ePowerTM GaN FETs are OFF when EN is low VDD standby and PWM fast shutdown input. Internal VDD is disabled when (SD/STB)
3
SD/STB L is pulled down or driven low. Internal pull-up resistor disables the standby function by default. If (SD/STB) is pulled low, the PWM inputs are immediately inhibited, and both power GaN FETs are switched OFF
4
VDD S Internal power supply referenced to AGND, connect a bypass capacitor from
7
VDD to AGND.
11 5
V
6
DRV S External 5 V power supply referenced to AGND, connect a bypass capacitor from VDRV to AGND.
12 6
RDRV G Insert a resistor between RDRV and VDRV to control the turn-on slew rate of the low-side FET.
13 1 2 3 4 5 7
AGND S Logic ground. AGND is internally connected to PGND.
8
PGND P Power ground. Connected to the source terminal of the low-side FET.
Transparent Top View 9
SW P Switching node. Connected to half-bridge power stage output.
10
VIN P Power DC input. Connected to drain terminal of the high-side FET. Connect power loop capacitors from VIN to PGND.
11
VPHASE S VPHASE is Kelvin connected to SW. Used as ground return for the bootstrap capacitor CBOOT.
12
RBOOT G Insert a resistor between RBOOT and VBOOT to control the turn-on slew rate of the high-side FET.
13
VBOOT S Floating bootstrap power supply referenced to VPHASE (=SW). Connect an external bootstrap capacitor, CBOOT, between VBOOT and VPHASE. Pin Type: P = Power, S = Bias Supplies, L = Logic Inputs/Outputs, G = Gate Drive Adjust Notes: • The standby function can be disabled by tying VDD to VDRV. In this case, only the PWM fast shutdown function is enabled. • AGND and PGND are internally connected. EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2026 | For more information: info@epc-co.com | 2
EPC23111
Figure 2: EPC23111 Quad Flat No-Lead (QFN) Package (Transparent Top View) EPC23111 Pinout Description Pin Pin Pin Name Type Description 1
PWM L Single pin PWM logic input referenced to AGND. Internal pull-down resistor is connected between PWM and AGND. SW follows PWM pin when EN is high
10 9 8 2
EN L Enable logic input referenced to AGND. Internal pull-down resistor is connected between EN and AGND. Both ePowerTM GaN FETs are OFF when EN is low VDD standby and PWM fast shutdown input. Internal VDD is disabled when (SD/STB)
3
SD/STB L is pulled down or driven low. Internal pull-up resistor disables the standby function by default. If (SD/STB) is pulled low, the PWM inputs are immediately inhibited, and both power GaN FETs are switched OFF
4
VDD S Internal power supply referenced to AGND, connect a bypass capacitor from
7
VDD to AGND.
11 5
V
6
DRV S External 5 V power supply referenced to AGND, connect a bypass capacitor from VDRV to AGND.
12 6
RDRV G Insert a resistor between RDRV and VDRV to control the turn-on slew rate of the low-side FET.
13 1 2 3 4 5 7
AGND S Logic ground. AGND is internally connected to PGND.
8
PGND P Power ground. Connected to the source terminal of the low-side FET.
Transparent Top View 9
SW P Switching node. Connected to half-bridge power stage output.
10
VIN P Power DC input. Connected to drain terminal of the high-side FET. Connect power loop capacitors from VIN to PGND.
11
VPHASE S VPHASE is Kelvin connected to SW. Used as ground return for the bootstrap capacitor CBOOT.
12
RBOOT G Insert a resistor between RBOOT and VBOOT to control the turn-on slew rate of the high-side FET.
13
VBOOT S Floating bootstrap power supply referenced to VPHASE (=SW). Connect an external bootstrap capacitor, CBOOT, between VBOOT and VPHASE. Pin Type: P = Power, S = Bias Supplies, L = Logic Inputs/Outputs, G = Gate Drive Adjust Notes: • The standby function can be disabled by tying VDD to VDRV. In this case, only the PWM fast shutdown function is enabled. • AGND and PGND are internally connected. EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2026 | For more information: info@epc-co.com | 2