Datasheet EPC23111 (Efficient Power Conversion) - 10

eGaN® IC DATASHEET
EPC23111
Figure 12: Simplified Circuit Diagram of VIN , VDRV , VDD , and VBOOT Gate Driver Power Supplies
The EPC23111 IC integrates both HS and LS FET gate drivers with low V LSG impedance and high pulse current push-pull NFET output stage. Figure 13 IN V is the simplified circuit diagram of the gate driver output stage. DRV V Sync DDON
Figure 13: Simplified Circuit Diagram of Gate Driver
Q boot OFF drive Q 1 OFF2 drive
Output Stage
VDD SD/STB VDDON VBOOTON AGND Internal Driving Q V SA QSB BOOT Circuit M V PO DRV VDD Q Optional standby CB1 function disable A MSO The internal supplies can be disabled to save quiescent power by turning MS1 off the series switch, QSA in Figure 12, with 0 V applied to the STB/SD pin to engage chip standby mode. In this mode, minimum current is drawn from the external VDRV supply while VDD is open circuit. Whatever charge The LS and HS gate drive voltage levels are derived from their respective remains within the VDD bypass capacitor will be discharged by the chip internal low-side (VDD) and high-side (VBOOT) power supplies. To ensure internal circuits by IDRV_Q. that the gate drive level (Q) is sufficiently close to VDD or VBOOT, an internal In the chip standby circuit, series switch (QSA) between VDRV and VDD is driving circuit is used to turn-on MPO. Here MPO and MSO work similarly to turned off by an internal standby circuit which itself derives its power from the half-bridge power stage Q1 and Q2 output FETs except all the circuits VIN such that the chip draws a current IVIN_disable from VIN when standby are internal to the IC. CB1 is a representation of the internal capacitors mode is engaged. The standby function requires a minimum input used in the gate driving circuitry. The gate driver output (Q) is designed voltage of VIN,min for the IC to be enabled. Below VIN,min, the pass-transistor to reach 100% duty cycle, therefore the PWM input pulse width has no between VDRV and VDD will be off. To disable the standby function, and maximum boundaries, as long as VDD and/or VBOOT are above the power thus extend the minimum operating voltage to VIN(Boot Mode)min = 0 V , tie on reset threshold limit. The high side circuit VBOOT can be supplied by an pins VDD and VDRV together. external floating voltage to al ow infinite ON time for the high-side FET. This is mandatory in boost converter applications, when DC input At initial powerup, CB1 is not yet ful y charged, consequently, propagation voltage, applied to SW pin, is lower than 13.5 V (= V delay (from PWM to SW) may increase, up to 250 ns. Only the first one, or INmin + |VHS_DS_ two pulses may be affected. Figure 14 il ustrates this behavior. Clamp_0V|). Moreover, in boost mode, if the feed-through operation mode is required, it is recommended to use a Schottky diode in paral el to the
Figure 14: Behavior before complete charging of internal gate
high-side GaN FET to mitigate the losses during non-switching operation
driver capacitors
(both PWM and EN OFF, or there is no VDD). The series connected high voltage synchronous bootstrap FET, QSB in Figure 12, between VDD and
VDD
VBOOT for the high-side floating bootstrap supply is activated only after the LS FET (Q2) is turned on to avoid overcharging during deadtime.
VBOOT
The use of GaN FET in the charging path eliminates reverse recovery and reduces power dissipation. Another advantage is the lower dropout
PWM
voltage of approximately 100 mV from the synchronous FET versus typical Si bootstrap diode voltage of 0.6 V. With synchronous charging
EN
VBOOT is maintained closer to the VDD voltage, al owing the HS FET gate drive circuit to have similar gate drive current and delay performance as
SW
the LS FET gate drive circuit. Normal operation CB1 of low side internal CB1 of high side internal circuit is charging. Low side circuit is charging. High power FET may turn ON side power FET may turn with a longer propagation ON with a longer delay (max 250 ns) propagation delay (max 250 ns) or slower dv/dt EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2026 | For more information: info@epc-co.com | 10