Datasheet EPC23111 (Efficient Power Conversion) - 8

eGaN® IC DATASHEET
EPC23111
Application Information
where Max T
General Description
J is specified at 125 °C and the ambient temperature is specified at 25 °C. The big variable in achieving the theoretical maximum The EPC23111 ePowerTM Stage IC integrates a half-bridge gate driver with power dissipation is RθJA, the thermal resistance from junction to ambient. internal high-side and low-side FETs. Integration is implemented using The EPC23111 package construction al ows two paral el paths of heat EPC’s proprietary GaN IC technology. The monolithic chip integrates dissipation where the bottom path goes from junction to metal ization input logic interface, level shifting, bootstrap charging and gate drive to lead-frame then the exposed pads at the bottom of the package. buffer circuits control ing high-side and low-side eGaN output FETs RθJB_bottom is determined by the three power bars (VIN, SW and PGND) configured as a half-bridge power stage. Robust level shifters from which are designed to al ow maximum contact area to the underlying low-side to high-side channels are designed to operate correctly with PCB pads. The total thermal resistance to ambient in this path of soft and hard switching conditions even at large negative clamped RθJA_bottom needs to add the heat dissipation from the PCB pads voltage and to avoid false trigger from fast dv/dt transients including through the multi-layer PCB construction then radiating to the ambient those driven by external sources or other phases. Internal circuits which is highly dependent on the airflow and forced cooling method. integrate the functions of charging and disabling of the logic and (See Figure 9). bootstrap power supplies. Protection features are added to protect the output FETs from
Figure 7: Functional Block Diagram
unwanted turn-on at low or even complete loss of supply voltages. The single chip GaN IC C is mounted inside a 3.5 x 5 mm Quad Flat No- DD 4 lead (QFN) package using a flip chip on lead- VDD 5 V
High-side
V 13 frame technique. This packaging structure DRV BOOT R R BOOT al ows very low parasitic inductance from the C UVLO BOOT 12 DRV Shutdown VIN Sync power terminals to the underlying PCB solder logic boot VIN 10 CBOOT pads. The exposed QFN pads are designed to Level Gate have at least 0.6 mm spacing between high and 65 kΩ Logic driver C shift IN + low voltage pins to meet IPC voltage creepage 3 DT VPHASE 11 SD/STB rule for 100 V. Another enhancement exposes + POR 9 the backside of the GaN IC die on the top side SW + of the package while completely encapsulating 2 EN Cross- V R DD DRV 6 over V the rest of the GaN IC die. This al ows a very low DRV Delay 1 PWM LO match Gate R thermal resistance path from the die junction to DRV level driver an attached heatsink which in effect increases shift 7 AGND PGND 8 the al owable power dissipation and thus higher current handling capability.
Output Current Rating
Power stage output current rating is best thought of as a figure
Figure 8: EPC23111 QFN package outline, pinouts and exposed
of merit for specified output current level that accounts for the
backside of the GaN IC die
maximum amount of power dissipation al owed from the IC. Total power dissipation from a power stage IC is tied to the application
Bottom
10 circuit topologies, output current demand, switching frequencies, 9 construction, operating temperature range, thermal management 8 technique and mechanical stress limit of the metal ization imposed 11 1213 by electromigration. The rating is related to the respective maximum current capability of the two integrated output FETs in the half-bridge
Top
power stage but not measured the same way as individual discrete FET. 1 For a power stage IC such as EPC23111, total power loss from the IC is 2 7 3 6 the sum of the two output FETs conduction, switching and deadtime
23111
4
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5 losses imposed by the application topologies at operating switching
YYYYA
frequencies as well as power losses from the gate drive and logic circuit. The maximum power dissipation is defined by the fol owing formula: Lot_Date Code Line 1 Lot_Date Code Line 2
Max PDiss = (Max TJ - TA) / RθJA
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