Datasheet TLC555 (Texas Instruments)
| Manufacturer | Texas Instruments |
| Description | LinCMOS Timer |
| Pages / Page | 41 / 1 — TLC555. TLC555 LinCMOS™ Timer. 1 Features. 3 Description. 2 Applications. … |
| Revision | H |
| File Format / Size | PDF / 1.4 Mb |
| Document Language | English |
TLC555. TLC555 LinCMOS™ Timer. 1 Features. 3 Description. 2 Applications. Device Information(1). PART NUMBER. PACKAGE. BODY SIZE (NOM)
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TLC555
SLFS043H – SEPTEMBER 1983 – REVISED AUGUST 2016
TLC555 LinCMOS™ Timer 1 Features 3 Description
• Very Low Power Consumption: The TLC555 is a monolithic timing circuit fabricated 1 using the TI LinCMOS™ process. The timer is fully – 1 mW Typical at VDD = 5 V compatible with CMOS, TTL, and MOS logic, and • Capable of Operation in Astable Mode operates at frequencies up to 2 MHz. Because of its • CMOS Output Capable of Swinging Rail to Rail high input impedance, this device uses smaller timing capacitors than those used by the NE555. As a • High Output Current Capability result, more accurate time delays and oscillations are – Sink: 100 mA Typical possible. Power consumption is low across the full – Source: 10 mA Typical range of power-supply voltage. • Output Fully Compatible With CMOS, TTL, and Like the NE555, the TLC555 has a trigger level equal MOS to approximately one-third of the supply voltage and a • Low Supply Current Reduces Spikes During threshold level equal to approximately two-thirds of Output Transitions the supply voltage. These levels can be altered by use of the control voltage terminal (CONT). When the • Single-Supply Operation From 2 V to 15 V trigger input (TRIG) falls below the trigger level, the • Functionally Interchangeable With the NE555; flip-flop is set and the output goes high. If TRIG is Has Same Pinout above the trigger level and the threshold input • ESD Protection Exceeds 2000 V Per MIL-STD- (THRES) is above the threshold level, the flip-flop is 883C, Method 3015.2 reset and the output is low. The reset input (RESET) can override all other inputs and can be used to • Available in Q-Temp Automotive initiate a new timing cycle. If RESET is low, the flip- – High-Reliability Automotive Applications flop is reset and the output is low. Whenever the – Configuration Control and Print Support output is low, a low-impedance path is provided between the discharge terminal (DISCH) and GND. – Qualification to Automotive Standards All unused inputs must be tied to an appropriate logic level to prevent false triggering.
2 Applications
• Precision Timing
Device Information(1)
• Pulse Generation
PART NUMBER PACKAGE BODY SIZE (NOM)
• Sequential Timing SOIC (8) 4.9 mm × 3.91 mm PDIP (8) 9.81 mm × 6.38 mm • Time Delay Generation TLC555C SOP (8) 6.20 mm × 5.30 mm • Pulse Width Modulation TSSOP (14) 5.00 mm × 4.40 mm • Pulse Position Modulation SOIC (8) 4.90 mm × 3.91 mm • Linear Ramp Generator TLC555I PDIP (8) 9.81 mm × 6.38 mm
Simplified Schematic
LCCC (20) 8.89 mm × 8.89 mm TLC555M CDIP (8) 9.60 mm × 6.67 mm CONT RESET 5 4 TLC555Q SOIC (8) 4.90 mm × 3.91 mm VDD 8 (1) For all available packages, see the orderable addendum at the end of the data sheet. R R1 6 THRES 3 R 1 OUT S R 2 TRIG R 7 DISCH 1 GND Copyright © 2016, Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. Document Outline 1 Features 2 Applications 3 Description Table of Contents 4 Revision History 5 Device Comparison Table 6 Pin Configuration and Functions 7 Specifications 7.1 Absolute Maximum Ratings 7.2 Recommended Operating Conditions 7.3 Thermal Information 7.4 Electrical Characteristics: VDD = 2 V for TLC555C, VDD = 3 V for TLC555I 7.5 Electrical Characteristics: VDD = 5 V 7.6 Electrical Characteristics: VDD = 15 V 7.7 Electrical Characteristics: VDD = 5 V 7.8 Typical Characteristics 8 Detailed Description 8.1 Overview 8.2 Functional Block Diagram 8.3 Feature Description 8.3.1 Monostable Operation 8.3.2 Astable Operation 8.3.3 Frequency Divider 8.4 Device Functional Modes 9 Application and Implementation 9.1 Application Information 9.2 Typical Applications 9.2.1 Missing-Pulse Detector 9.2.1.1 Design Requirements 9.2.1.2 Detailed Design Procedure 9.2.1.3 Application Curve 9.2.2 Pulse-Width Modulation 9.2.2.1 Design Requirements 9.2.2.2 Detailed Design Procedure 9.2.2.3 Application Curve 9.2.3 Pulse-Position Modulation 9.2.3.1 Design Requirements 9.2.3.2 Detailed Design Procedure 9.2.3.3 Application Curve 9.2.4 Sequential Timer 9.2.4.1 Design Requirements 9.2.4.2 Detailed Design Procedure 9.2.4.3 Application Curve 10 Power Supply Recommendations 11 Layout 11.1 Layout Guidelines 11.2 Layout Example 12 Device and Documentation Support 12.1 Receiving Notification of Documentation Updates 12.2 Community Resources 12.3 Trademarks 12.4 Electrostatic Discharge Caution 12.5 Glossary 13 Mechanical, Packaging, and Orderable Information
TLC555
SLFS043H – SEPTEMBER 1983 – REVISED AUGUST 2016
TLC555 LinCMOS™ Timer 1 Features 3 Description
• Very Low Power Consumption: The TLC555 is a monolithic timing circuit fabricated 1 using the TI LinCMOS™ process. The timer is fully – 1 mW Typical at VDD = 5 V compatible with CMOS, TTL, and MOS logic, and • Capable of Operation in Astable Mode operates at frequencies up to 2 MHz. Because of its • CMOS Output Capable of Swinging Rail to Rail high input impedance, this device uses smaller timing capacitors than those used by the NE555. As a • High Output Current Capability result, more accurate time delays and oscillations are – Sink: 100 mA Typical possible. Power consumption is low across the full – Source: 10 mA Typical range of power-supply voltage. • Output Fully Compatible With CMOS, TTL, and Like the NE555, the TLC555 has a trigger level equal MOS to approximately one-third of the supply voltage and a • Low Supply Current Reduces Spikes During threshold level equal to approximately two-thirds of Output Transitions the supply voltage. These levels can be altered by use of the control voltage terminal (CONT). When the • Single-Supply Operation From 2 V to 15 V trigger input (TRIG) falls below the trigger level, the • Functionally Interchangeable With the NE555; flip-flop is set and the output goes high. If TRIG is Has Same Pinout above the trigger level and the threshold input • ESD Protection Exceeds 2000 V Per MIL-STD- (THRES) is above the threshold level, the flip-flop is 883C, Method 3015.2 reset and the output is low. The reset input (RESET) can override all other inputs and can be used to • Available in Q-Temp Automotive initiate a new timing cycle. If RESET is low, the flip- – High-Reliability Automotive Applications flop is reset and the output is low. Whenever the – Configuration Control and Print Support output is low, a low-impedance path is provided between the discharge terminal (DISCH) and GND. – Qualification to Automotive Standards All unused inputs must be tied to an appropriate logic level to prevent false triggering.
2 Applications
• Precision Timing
Device Information(1)
• Pulse Generation
PART NUMBER PACKAGE BODY SIZE (NOM)
• Sequential Timing SOIC (8) 4.9 mm × 3.91 mm PDIP (8) 9.81 mm × 6.38 mm • Time Delay Generation TLC555C SOP (8) 6.20 mm × 5.30 mm • Pulse Width Modulation TSSOP (14) 5.00 mm × 4.40 mm • Pulse Position Modulation SOIC (8) 4.90 mm × 3.91 mm • Linear Ramp Generator TLC555I PDIP (8) 9.81 mm × 6.38 mm
Simplified Schematic
LCCC (20) 8.89 mm × 8.89 mm TLC555M CDIP (8) 9.60 mm × 6.67 mm CONT RESET 5 4 TLC555Q SOIC (8) 4.90 mm × 3.91 mm VDD 8 (1) For all available packages, see the orderable addendum at the end of the data sheet. R R1 6 THRES 3 R 1 OUT S R 2 TRIG R 7 DISCH 1 GND Copyright © 2016, Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. Document Outline 1 Features 2 Applications 3 Description Table of Contents 4 Revision History 5 Device Comparison Table 6 Pin Configuration and Functions 7 Specifications 7.1 Absolute Maximum Ratings 7.2 Recommended Operating Conditions 7.3 Thermal Information 7.4 Electrical Characteristics: VDD = 2 V for TLC555C, VDD = 3 V for TLC555I 7.5 Electrical Characteristics: VDD = 5 V 7.6 Electrical Characteristics: VDD = 15 V 7.7 Electrical Characteristics: VDD = 5 V 7.8 Typical Characteristics 8 Detailed Description 8.1 Overview 8.2 Functional Block Diagram 8.3 Feature Description 8.3.1 Monostable Operation 8.3.2 Astable Operation 8.3.3 Frequency Divider 8.4 Device Functional Modes 9 Application and Implementation 9.1 Application Information 9.2 Typical Applications 9.2.1 Missing-Pulse Detector 9.2.1.1 Design Requirements 9.2.1.2 Detailed Design Procedure 9.2.1.3 Application Curve 9.2.2 Pulse-Width Modulation 9.2.2.1 Design Requirements 9.2.2.2 Detailed Design Procedure 9.2.2.3 Application Curve 9.2.3 Pulse-Position Modulation 9.2.3.1 Design Requirements 9.2.3.2 Detailed Design Procedure 9.2.3.3 Application Curve 9.2.4 Sequential Timer 9.2.4.1 Design Requirements 9.2.4.2 Detailed Design Procedure 9.2.4.3 Application Curve 10 Power Supply Recommendations 11 Layout 11.1 Layout Guidelines 11.2 Layout Example 12 Device and Documentation Support 12.1 Receiving Notification of Documentation Updates 12.2 Community Resources 12.3 Trademarks 12.4 Electrostatic Discharge Caution 12.5 Glossary 13 Mechanical, Packaging, and Orderable Information