Datasheet CD4098BMS (Intersil)

ManufacturerIntersil
DescriptionCMOS Dual Monostable Multivibrator
Pages / Page11 / 1 — Features. Description. • High Voltage Type (20V Rating). • …
Revision2017-12-22
File Format / SizePDF / 327 Kb
Document LanguageEnglish

Features. Description. • High Voltage Type (20V Rating). • Retriggerable/Resettable Capability

Datasheet CD4098BMS Intersil, Revision: 2017-12-22

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DATASHEET CD4098BMS FN3332 CMOS Dual Monostable Multivibrator Rev 0.00 December 1992
Features Description • High Voltage Type (20V Rating)
CD4098BMS dual monostable multivibrator provides stable retriggerable/resettable one shot operation for any fixed volt-
• Retriggerable/Resettable Capability
age timing application.
• Trigger and Reset Propagation Delays Independent of
An external resistor (RX) and an external capacitor (CX)
RX, CX
control the timing for the circuit. Adjustment of RX and CX
• Triggering from Leading or Trailing Edge
provides a wide range of output pulse widths from the Q and Q terminals. The time delay from trigger input to output
• Q and Q Buffered Outputs Available
transition (trigger propagation delay) and the time delay from
• Separate Resets
reset input to output transition (reset propagation delay) are
• Wide Range of Output Pulse Widths
independent of RX and CX.
• 100% Tested for Quiescent Current at 20V
Leading edge triggering (+TR) and trailing edge triggering (-TR) inputs are provided for triggering from either edge of
• 5V, 10V and 15V Parametric Ratings
an input pulse. An unused +TR input should be tied to VSS.
• Standardized Symmetrical Output Characteristics
An unused -TR input should be tied to VDD. A RESET (on low level) is provided for immediate termination of the output
• Maximum Input Current of 1

A at 18V Over Full Pack-
pulse or to prevent output pulses when power is turned on.
age Temperature Range; 100nA at 18V and +25oC
An unused RESET input should be tied to VDD. However, if
• Noise Margin (Over Full Package/Temperature Range)
an entire section of the CD4098BMS is not used, its RESET
- 1V at VDD = 5V
should be tied to VSS. See Table 9.
- 2V at VDD = 10V
In normal operation the circuit triggers (extends the output
- 2.5V at VDD = 15V
pulse one period) on the application of each new trigger pulse. For operation in the non-retriggerable mode, Q is
• Meets All Requirements of JEDEC Tentative Standard
connected to -TR when leading edge triggering (+TR) is
No. 13B, “Standard Specifications for Description of
used or Q is connected to +TR when trailing edge triggering
‘B’ Series CMOS Devices”
(-TR) is used.
Applications
The time period (T) for this multivibrator can be approximated by: TX = 1/2RXCX for CX 3 0.01F. Time
• Pulse Delay and Timing
periods as a function of RX for values of CX and VDD are
• Pulse Shaping
given in Figure 8. Values of T vary from unit to unit and as a function of voltage, temperature, and RXCX.
Astable Multivibrator
The minimum value of external resistance, RX, is 5k. The maximum value of external capacitance, CX, is 100F. Figure 9 shows time periods as a function of CX for values of RX and VDD.
Pinout CD4098BMS
The output pulse width has variations of 2.5% typically, TOP VIEW over the temperature range of -55oC to +125oC for CX = 1000pF and RX = 100k.
CX1 1 16 VDD
For power supply variations of 5%, the output pulse width
RXCX (1) 2 15 CX2
has variations of 0.5% typically, for VDD = 10V and 15V
RESET (1) 3 14 RXCX (2)
and 1% typical y, for VDD = 5V at CX = 1000pF and RX = 5k.
+TR (1) 4 13 RESET (2) -TR (1) 5 12 +TR (2)
The CD4098BMS is supplied in these 16-lead outline packages:
Q1 6 11 -TR (2)
Braze Seal DIP H4T
Q1 7 10 Q2
Frit Seal DIP H1F Ceramic Flatpack H6W
VSS 8 9 Q2 TERMINALS 1, 8, 15 ARE ELECTRICALLY CONNECTED INTERNALLY
FN3332 Rev 0.00 Page 1 of 11 December 1992
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