Datasheet BC3602 (Holtek) - 10
| Manufacturer | Holtek |
| Description | Sub-1GHz Low RX Current FSK/GFSK RF Transceiver |
| Pages / Page | 61 / 10 — BC3602. • IRQ1: Interrupt Control Register 1. Bit. RXTO. RXFFOW. … |
| File Format / Size | PDF / 1.3 Mb |
| Document Language | English |
BC3602. • IRQ1: Interrupt Control Register 1. Bit. RXTO. RXFFOW. RXDETS[1:0]. IRQCPOR. IRQPOR. • IRQ2: Interrupt Control Register 2
Model Line for this Datasheet
Text Version of Document
BC3602 • IRQ1: Interrupt Control Register 1 Bit 7 6 5 4 3 2 1 0
Name RXTO RXFFOW — — RXDETS[1:0] IRQCPOR IRQPOR R/W R R — — R/W R/W R/W Reset 0 0 0 0 1 0 0 1 Bit 7
RXTO
: RX time-out flag 0: RX time-out does not occur 1: RX time-out occurs This flag will be set high by hardware when the RX time-out condition occurs and automatically cleared when a Light Sleep strobe command is received, when the device enters the RX continuous mode, when WOR/WOT wake up occurs or when the device enters the ARK TX/RX mode. Bit 6
RXFFOW
: RX FIFO overwrite flag 0: RX FIFO overwrite does not occur 1: RX FIFO overwrite occurs This flag will be set high by hardware when the RX FIFO overwrite condition occurs and automatically cleared when a RX FIFO reset strobe command or a RX strobe command is received. Bit 5~4 Reserved, must be “00” Bit 3~2
RXDETS[1:0]
: RX detect selection 00: Detect carry 01: Detect preamble 10/11: Detect SYNCWORD Bit 1
IRQCPOR
: IRQ flags clearing polarity selection 0: IRQ flags are cleared by writing 0 to the corresponding bits 1: IRQ flags are cleared by writing 1 to the corresponding bits Bit 0
IRQPOR
: IRQ signal polarity selection 0: Active low 1: Active high When an IRQ flag in the IRQ3 register is set high and the corresponding IRQ function is enabled, the active level of the IRQ signal is determined by this configuration.
• IRQ2: Interrupt Control Register 2 Bit 7 6 5 4 3 2 1 0
Name ARKTFIE ATRCTIE FIFOLTIE RXERRIE RXDETIE CALCMPIE RXCMPIE TXCMPIE R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7
ARKTFIE
: ARK TX Failure IRQ Enable 0: Disable 1: Enable Bit 6
ATRCTIE
: ATR Cycle Timer IRQ Enable 0: Disable 1: Enable Bit 5
FIFOLTIE
: FIFO Low Threshold IRQ Enable 0: Disable 1: Enable Rev. 1.00 10 July 29, 2019 Document Outline Features General Description Block Diagram Pin Assignment Pin Description Absolute Maximum Ratings D.C. Characteristics A.C. Characteristics Memory Mapping Control Register Access SFR Mapping and Bit Definition Common Area Control Register Bank 0 Control Registers Bank 1 Control Registers Bank 2 Control Registers Special Function Description Sub-1GHz RF Transceiver Serial Interface System Clock Frequency Synthesizer Modulator State Machine Calibration AGC & RSSI Packet Handler FIFO Operation Modes Receiving Packet Judgement Continuous RX Mode ARK Mode: Auto-Resend and Auto-Ack ATR Mode: Auto-Transmit-Receive Message Flowchart Examples Abbreviation Application Circuits Package Information SAW Type 24-pin QFN (3mm×3mm×0.55mm) Outline Dimensions
Name RXTO RXFFOW — — RXDETS[1:0] IRQCPOR IRQPOR R/W R R — — R/W R/W R/W Reset 0 0 0 0 1 0 0 1 Bit 7
RXTO
: RX time-out flag 0: RX time-out does not occur 1: RX time-out occurs This flag will be set high by hardware when the RX time-out condition occurs and automatically cleared when a Light Sleep strobe command is received, when the device enters the RX continuous mode, when WOR/WOT wake up occurs or when the device enters the ARK TX/RX mode. Bit 6
RXFFOW
: RX FIFO overwrite flag 0: RX FIFO overwrite does not occur 1: RX FIFO overwrite occurs This flag will be set high by hardware when the RX FIFO overwrite condition occurs and automatically cleared when a RX FIFO reset strobe command or a RX strobe command is received. Bit 5~4 Reserved, must be “00” Bit 3~2
RXDETS[1:0]
: RX detect selection 00: Detect carry 01: Detect preamble 10/11: Detect SYNCWORD Bit 1
IRQCPOR
: IRQ flags clearing polarity selection 0: IRQ flags are cleared by writing 0 to the corresponding bits 1: IRQ flags are cleared by writing 1 to the corresponding bits Bit 0
IRQPOR
: IRQ signal polarity selection 0: Active low 1: Active high When an IRQ flag in the IRQ3 register is set high and the corresponding IRQ function is enabled, the active level of the IRQ signal is determined by this configuration.
• IRQ2: Interrupt Control Register 2 Bit 7 6 5 4 3 2 1 0
Name ARKTFIE ATRCTIE FIFOLTIE RXERRIE RXDETIE CALCMPIE RXCMPIE TXCMPIE R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7
ARKTFIE
: ARK TX Failure IRQ Enable 0: Disable 1: Enable Bit 6
ATRCTIE
: ATR Cycle Timer IRQ Enable 0: Disable 1: Enable Bit 5
FIFOLTIE
: FIFO Low Threshold IRQ Enable 0: Disable 1: Enable Rev. 1.00 10 July 29, 2019 Document Outline Features General Description Block Diagram Pin Assignment Pin Description Absolute Maximum Ratings D.C. Characteristics A.C. Characteristics Memory Mapping Control Register Access SFR Mapping and Bit Definition Common Area Control Register Bank 0 Control Registers Bank 1 Control Registers Bank 2 Control Registers Special Function Description Sub-1GHz RF Transceiver Serial Interface System Clock Frequency Synthesizer Modulator State Machine Calibration AGC & RSSI Packet Handler FIFO Operation Modes Receiving Packet Judgement Continuous RX Mode ARK Mode: Auto-Resend and Auto-Ack ATR Mode: Auto-Transmit-Receive Message Flowchart Examples Abbreviation Application Circuits Package Information SAW Type 24-pin QFN (3mm×3mm×0.55mm) Outline Dimensions
