After the terget device answered with DEVSEL#, the terget device confirms IRDY# is asserted (Write data is valid.), and takes data in the target device. At the same time, the target device knows that the transfer is the last cycle because of FRAME# is deasserted and IRDY# is asserted whitch means current data is last transfer.
When the last data is taken in, the terget device drives DEVSEL# and TRDY# to be deasserted, and DEVSEL# and TRDY# are released at the next clock, and the target device finishes the bus cycle.
After two clocks from start of the bus cycle, terget device puts read data on the AD bus, and assert TRDY#. At the next clock, terget device checks IRDY#. If the IRDY# is asserted (initiater can accept read data.), the data transfer is completed. And FRAME# is deasserted, it means current data is last transfer. Terget device detects it and terminates the bus transaction.
After last data is transferred, terget device drives DEVSEL# and TRDY# to deassert, and DEVSEL# and TRDY# are released at the next clock, and the bus transaction is terminated.
Write Cycle (Burst Transfer)
PCI is designed to show performance most at burst transfer. It can be imagined easily from the address and data as well being multiplexed. At the burst transfer, terget address is only specified at start of data transfer is sufficient. PCI reduces the number of signal lines by this, and also reduces the stability of the operation and a cost.
Fast Back to Back Transaction
Usually, one clock of idol cycle exists between the bus cycles (transaction) at least. The idol cycle is a buffer time to prevent each output from colliding, however, it can be omitted when device switching is not occured between the bus cycles.
The Operation of the I/O Board : STATE
The Design Rule Violation
Well, the circuit diagram is simplified in this experiment by partly omitting the function required as a PCI device. I explain about the omitted function, and the evil by that. It will specially never cause a trouble as an experiment made with a PC though they are the contents which faint when the designer of the normal PCI device sees it.
There is no configration register.
The terget address is being decoded fixedly in this board without mounting configuration register. You must set up terget address so that the conflict of the resource may not occur because the existence of the device isn't recognized by a system. A PCI board with a DIP switch will be laughed :-)
There is no funftion of parity generation and check
Upper 16 bits of address is not decoded
Building the PCI Board
Circuit Diagram | PLD source fileThe proto-board for PCI is MCC-331(Sunhayato). It has a mount bracket, so that it is easy to use.
PLD should use the speed grade of 7ns or faster. Even 7ns doesn't satisfy specs with the specs of the bus timing. But, because to obtain the PLD faster than 5ns is difficult, it is used in consideration of the margin. (It will no problem.)
Any other parts except will not need to select manufacturer because they are the just ordinary. Inputs and outputs are 16bit for each because it lacked the mounting space of the connector this time though they were the places where 32bit wanted it respectively.
Because it is a digital circuit, I think that it never takes care of building. Because there is many wires, UEW is suitable for wiring. Don't use any other wire because it will become like a mountain. That you must be the most careful is not to mistake wiring. So it is easy to mistake because a terminal number is discontinuous at voltage key of the edge connector. I actually mistook some times, too. :-) Especially, a mistake of the power supply pins can destroy main board. Moreover, you should reinforce a power supply line fully because it operates at high speed of maximum 33MHz.
Test and Result
When for example F300h is set, this board responds to the access from F300h to F303h,
Well, let's go with the performance check if you can confirm that it operates completely. Performance test counts cycles per second that access terget device with I/O string operating instructions. The result is as follows:
Though it is natural, PCI showed an overwhelming speed in comparison with ISA. As for the write operation, 6clks/cycle, a read operation become 9clks/cycle's from the calculation of the number of clocks. But, because they are 3clks and 4clks respectively by the theory value, it will able to be said that a transfer rate doesn't rise that much, too. (Bus idol time is long.) Time loss in the HOST-PCI bridge thinks this a cause. However, PCI is designed so that the best performance may appear in the burst transfer. It is inevitable that performance is poor in the single transfer.
And, there is a difference in the speed which is near to the double in 16bit access and 8bit access in ISA bus. As for this, an I/O cycle is reduced when device responds as a 16 bit device in the ISA bus. It is good when even a 8bit device is made to operate -IOCS16 when it wants to increse a speed in ISA bus.
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