The DI's Figure 1 schematic has been redrawn to emphasize the positioning of the U1 regulator in the A1 op amp's feedback loop. The V_DAC signal controls U1 while ignoring its internal reference voltage

Authors	Christopher Paul
Main Document	Article «Ignoring the regulator's reference redux»
Description	Figure 1
File Format / Size	PDF / 16 Kb
Document Language	English

Other Materials from the Main Document

Figure 1. The DI's Figure 1 schematic has been redrawn to emphasize the positioning of the U1 regulator in the A1 op amp's feedback loop. The V_DAC signal controls U1 while ignoring its internal reference voltage
Figure 2. Each PWM input is an 8-bit DAC. V_REF should be at least 3.0 V to support the SN74AC04 output resistances calculable from its datasheet. C_A and C₁-C₃ are COG/NPO

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