Application Note AN143
Michel Azarian, Will Ezel
Presented is a simple model that can be used to accurately predict the level of reference spurs due to charge pump and/or op amp leakage current in a PLL system. Knowing how to predict these levels helps pick loop parameters wisely during the early stages of a PLL system design.
The phase locked loop (PLL) is a negative feedback system that locks the phase and frequency of a higher frequency device (usually a voltage controlled oscillator, VCO) whose phase and frequency are not very stable over temperature and time to a more stable and lower frequency device (usually a temperature compensated or oven controlled crystal oscillator, TCXO or OCXO). As a black box, the PLL can be viewed as a frequency multiplier.
A PLL is employed when there is the need for a high frequency local oscillator (LO) source. Example applications are numerous and include wireless communications, medical devices and instrumentation.
Figure shows the building blocks of a PLL system used for generating an LO signal. The PLL integrated circuit (IC) usually contains all clock dividers (R and N), phase/ frequency detector (PFD) and the charge pump, represented by the two current sources, ICP_UP and ICP_DN.
The VCO output is compared to the reference clock (the OCXO output here) after both signals are divided down in frequency by their respective integer dividers (N and R, respectively). The PFD block controls the charge pump to sink or source current pulses at the fPFD rate into the loop filter to adjust the voltage on the tuning port of the VCO (V_TUNE) until the outputs of the clock dividers are equal in frequency and are in phase. When these are equal, it is said that the PLL is locked. ...
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Basic Building Blocks of a PLL