Gated oscillator holds last level

Einar Abell

EDN

This Design Idea is a gated oscillator with the unusual (unique?) characteristic of stopping in its current state rather than being forced high or low. Unlike a conventional gated oscillator, this one both starts and stops in its existing state whether high or low. Gating a conventional oscillator may cause the output to change state with the control signal, either at the start or the end (or both). Also, it will not produce any truncated pulses.

The circuit consists of the conventional CMOS oscillator, but with the feedback split into a separate positive path (the non-inverting U2), and a controlled path (the XOR gate U1) that can be either positive or negative, depending on the state of the control input.

Gated oscillator holds last level

When the control input is high, the XOR is an inverter, and its output will be the reverse of U2's output, allowing C1 to charge or discharge through R1 until the threshold of U2 is reached ( ½ V+) and the output switches, reversing the process for the next half-cycle. When the control input goes low, the XOR gate becomes a non-inverter, and only positive feedback is present. C1 now discharges through R1, and the output remains in whatever state it was in. When the control input goes high again, the oscillation starts from whatever state this was.

Another unusual feature of this circuit is that it can act as a frequency divider. If the control input is a repetitive signal, and R1 and C1 are chosen such that the oscillator output changes state just once when the input is high, the output frequency will be one half the input.

R2 limits the current into the protection diodes of U2; it is most conveniently made equal to R1, but can range from 1 kΩ to several megohms. U2 can be an EXOR gate with one input grounded, or whatever form of buffer is available.

Oscillation frequency is approximately 1.4·R1·C1.

This switched feedback method will also work if U2 is a Schmitt trigger; connect C1 to ground instead of the output, and remove R2.

EDN

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