Proper component selection can help reduce startup time for gated oscillators.
Gated oscillators always present the typical problem of having a delay when a digital input control signal enables its oscillation. This delay happens because the timing capacitor starts discharging from VDD to start oscillating between two thresholds points known as VT+, and VT–. This causes the oscillator to have a time delay before it starts oscillating at its expected base frequency. The delay affects precision in timing measurements.
|Figure 1.||This is a classic logic oscillator. The timing diagram is to the right with time periods T0, T1, and T2.|
Figure 1 shows a classic gated oscillator with its respective timing diagram. When the control signal goes from low to high logic, capacitor C discharges trough resistor R from VDD to VT–, therefore causing a delay called T0. In this case, Equation 1 defines the voltage across resistor R during the T0 interval:
Solving for T0, we get:
where VDD is the NAND’s gate output voltage and VR is the negative threshold voltage VT– that resistor R will reach. Thus, we get T0 in Equation 3:
The startup delay T0 can be eliminated with the solution shown in Figure 2. When the control signal input is low, capacitor C will hold its voltage a few millivolts less than the positive threshold voltage (VT+) by using a trim pot that will set and hold that voltage. The switching diode D1, will hold the capacitor’s voltage below to VT+, i.e., < 2.8 V, to avoid triggering the gate. The voltage applied to the capacitor with the trim pot and diode D1 must be less than VT+ plus VR, i.e.,
As you can see in Figure 2, when the control signal goes high, the output on NAND gate is low, causing capacitor C to start discharging from VT+ to VT–, thanks to the reverse bias in diode D1. The capacitor then will start charging and discharging within VT+ and VT– continuously (Fig. 3). When the control signal goes high, the capacitor will go back to its original voltage equal to VC.
|Figure 2.||This CMOS gated oscillator has no startup delay.|
During the discharging period T2, the switching diode D1 (1N4148 or 1N4150) is reverse-biased and will disconnect the trim pot’s voltage to allow C to discharge up to VT–. Equations 4 and 5 define the timing periods for charging T1 and discharging T2:
The output frequency FO is defined by Equation 6:
According to the 74HC132 datasheet, when these NAND gates are biased with VDD = 5 V, its threshold voltages are VT– = 1.8 V, and VT+ = 2.8 V. Substituting these values into Equation 6, we get a constant k in Equation 7:
Notice that the precision of your output frequency depends on the tolerance of the components in the RC network. The resistor tolerance must be 1%. The capacitor tolerance must be 5% or better.
|Figure 3.||The scope image shows the CMOS gated oscillator with no startup delay.
The yellow line is the control signal input, the blue line is the capacitor voltage,
and the violet line is the NAND gate output.
Figure 3 presents the scope image in which you can see how the capacitor starts discharging from VT+, (not from VDD), therefore not causing a delay in the output signal frequency FO.
A gated oscillator like this only has a 20-ns delay to start oscillating, defined by the gate propagation delay time TPD. In this case, we used the Schmitt trigger NAND gate 74HC132. It’s recommended to use the other NAND gates available as buffers to isolate the RC network.
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