Peter Clarke
In a return to the 20th century days of electromechanical computation IBM and STMicroelectronics are working on a project to enable a low-power processor made from nanometer-scale mechanical relays.
The European Commission likes the idea and has put IBM Research Zurich in charge of a European research project that aims to produce a logic process that is based on nanometer-scale relays that remain compatible with conventional CMOS transistor logic. The advantage of such a system would be much lower off-state power consumption as leakage current would be considerably reduced.
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| Mechanical relay as replacement for transistor. Source: NEMIAC |
Alongside IBM and STMicroelectronics NV (Geneva, Switzerland) are academic researchers from the Ecole Polytechnique Federale de Lausanne, Kungliga Tekniska Hoegskolan (KTH), and the universities of Bristol and Lancaster.
The three-year collaborative research project has a budget of 3.96 million euro (about $5.0 million) of which the European Commission is providing 2.44 million euro (about $3.1 million).
The motivation for the research is that as transistors have been miniaturized leakage power consumption is becoming as large as active power consumption and this is a particular issue for emerging applications such as autonomous sensors nodes, wireless communications and mobile computing.
The NEMIAC (Nano-Electro-Mechanical Integration And Computation) project aims to develop a process based on what it calls nano-electromechanical (NEMS) switches suitable for embedded systems and offering 3-D integration with CMOS. The researchers are being asked to show a magnitude improvement in energy efficiency with no performance penalty compared with solid-state. The process is also expected to have higher radiation resistance and higher temperature operation than CMOS.
The relays are expected to have a footprint of less than 3-micron by 3-micron and demonstrate a switching time of the order of 10 nanoseconds. Prooving the reliability under billions of switching operations will be an important task prior to commercial deployment.
The project is expected to produce a number of digital logic designs as proof of the process and innovative circuit architectures for low-power applications.
In parallel design and simulation methodologies are going to be developed to aid exploration of the design-space and demonstrate the feasibility of a small microprocessor.
