Freescale Expands Its 16-Bit HCS12 MCU Family

The S12X family will retain the low cost, power consumption, EMC and code-size efficiency advantages currently enjoyed by users of the existing 16-bit HCS12 MCU family. Based around an enhanced HCS12 core, the S12XD family is designed to deliver 2 to 5 times the performance of a 25 MHz HCS12 whilst retaining a high degree of pin and code compatibility with the HCS12. The S12XD family introduces the performance boosting XGATE module. Using enhance DMA functionality, this parallel processing module offloads the CPU by providing high speed data processing and transfer between peripheral modules, RAM and I/O ports. Providing up to 80MIPS of performance additional to the CPU, the XGATE can access all peripherals and the RAM block.

The MC9S12XDP512 is composed of standard on-chip peripherals including 512K bytes of Flash EEPROM, 32K bytes of RAM, 4K bytes of EEPROM, six asynchronous serial communication interfaces (SCI), three serial peripheral interface (SPI), an 8-channel IC/OC enhanced capture timer, an 8-channel, 10-bit analog-to-digital converter, a 16-channel, 10-bit analog-to-digital converter, an 8-channel pulse-width modulator (PWM), five CAN 2.0A, B software compatible modules (MSCAN12), two Inter-IC Bus blocks and a Periodic Interrupt Timer. The MC9S12XDP512 has full 16-bit data paths throughout. The non-multiplexed expanded bus interface available on the 144-pin versions allows an easy interface to external memories. The MC9S12XDP512 will be available in 144-pin LQFP with external bus interface and in 112-pin LQFP or 80-pin QFP package without external bus interface.

MC9S12XDP512 Features

• HCS12X Core
  • 16-bit HCS12X CPU
    1. Upward compatible with HCS12 instruction set
    2. Interrupt stacking and programmer's model identical to HCS12
    3. Instruction queue
    4. Enhanced indexed addressing
    5. Enhanced instruction set
  • EBI (External Bus Interface)
  • MMC (Module Mapping Control)
  • INT (Interrupt Controller)
  • DBG (Debug module to monitor HCS12X CPU and XGATE bus activity)
  • BDM (Background Debug Mode)
• XGATE
  • Peripheral Co-Processor
  • Parallel processing module offloads the CPU by providing high speed data processing transfer between peripheral modules, RAM and I/O ports
  • Data transfer between Flash EEPROM, peripheral modules and I/O ports
• PIT Periodic Interrupt Timer
  • Four Timers with independent time-out periods
  • Time-out periods selectable between 1 and 2²⁴ bus clock cycles
• CRG
  • Low Noise/Low Power Pierce oscillator
  • PLL
  • COP watchdog
  • Real time interrupt
  • Clock monitor
  • Fast wake-up from STOP mode