12-Bit Incremental ADC Datasheet ADCINC12 V 5.3 (Cypress)
| Manufacturer | Cypress |
| Description | The ADCINC12 User Module implements a 12-bit incremental A/D that generates a 12-bit, full-scale 2's complement output (+2047 to -2048 count range) with several input ranges to select from. Input voltage ranges, including rail-to-rail, may be measured by configuring the proper reference voltage and analog ground. It supports sample rates from 7.8 sps to 480 sps |
| Pages / Page | 23 / 1 — 12-Bit Incremental ADC Datasheet ADCINC12 V 5.3. PSoC® Blocks. API Memory … |
| File Format / Size | PDF / 394 Kb |
| Document Language | English |
12-Bit Incremental ADC Datasheet ADCINC12 V 5.3. PSoC® Blocks. API Memory (Bytes). Pins (per. Resources. Digital
Text Version of Document
12-Bit Incremental ADC Datasheet ADCINC12 V 5.3
001-13252 Rev. *H 12-Bit Incremental ADC Copyright © 2002-2013 Cypress Semiconductor Corporation. All Rights Reserved.
PSoC® Blocks API Memory (Bytes) Pins (per Resources Digital Analog CT Analog SC Flash RAM External I/O)
CY8C29/27/24/22x13, 2 0 1 224 6 1 CY8C23x33, CY8CLED04/08/16, CY8C28x45, CY8C28x43, CY8C28x52 CYWUSB6953 0 0 0 25 0 1 to 4 See AN2239, ADC Selection Guide for other converters.
Features and Overview
12-bit resolution, 2’s complement Sample rate from 7.8 sps to 480 sps Input range AGND +/- VRef Provides normal mode rejection of high frequency harmonics Internal or external clock The ADCINC12 User Module implements a 12-bit incremental A/D that generates a 12-bit, full-scale 2’s complement output (+2047 to -2048 count range) with several input ranges to select from. Input voltage ranges, including rail-to-rail, may be measured by configuring the proper reference voltage and analog ground. It supports sample rates from 7.8 sps to 480 sps. The ADCINC12 programming interface allows you to select from 0 to 255 samples, where zero specifies continuous sampling. The ADCINC12 is an integrating ADC that provides removal of higher frequencies. Optimum rejection of 50 Hz, 60 Hz, and any harmonics of these two frequencies (normal mode rejection) can be achieved by setting the sample window to 100 ms (sample rate to 9.84 sps). The CPU load varies with the input level.
Cypress Semiconductor Corporation
• 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Document Number: 001-13252 Rev. *H Revised May 14, 2013 Document Outline Features and Overview Functional Description Example 1 Example 2 Incremental ADC DC and AC Electrical Characteristics CY8C29xxx Typical Performance Placement Parameters and Resources Example 1 Example 2 Interrupt Generation Control Application Programming Interface ADCINC12_Start ADCINC12_SetPower ADCINC12_Stop ADCINC12_GetSamples ADCINC12_StopAD ADCINC12_fIsDataAvailable ADCINC12_iGetData ADCINC12_ClearFlag Sample Firmware Source Code Configuration Registers Version History
001-13252 Rev. *H 12-Bit Incremental ADC Copyright © 2002-2013 Cypress Semiconductor Corporation. All Rights Reserved.
PSoC® Blocks API Memory (Bytes) Pins (per Resources Digital Analog CT Analog SC Flash RAM External I/O)
CY8C29/27/24/22x13, 2 0 1 224 6 1 CY8C23x33, CY8CLED04/08/16, CY8C28x45, CY8C28x43, CY8C28x52 CYWUSB6953 0 0 0 25 0 1 to 4 See AN2239, ADC Selection Guide for other converters.
Features and Overview
12-bit resolution, 2’s complement Sample rate from 7.8 sps to 480 sps Input range AGND +/- VRef Provides normal mode rejection of high frequency harmonics Internal or external clock The ADCINC12 User Module implements a 12-bit incremental A/D that generates a 12-bit, full-scale 2’s complement output (+2047 to -2048 count range) with several input ranges to select from. Input voltage ranges, including rail-to-rail, may be measured by configuring the proper reference voltage and analog ground. It supports sample rates from 7.8 sps to 480 sps. The ADCINC12 programming interface allows you to select from 0 to 255 samples, where zero specifies continuous sampling. The ADCINC12 is an integrating ADC that provides removal of higher frequencies. Optimum rejection of 50 Hz, 60 Hz, and any harmonics of these two frequencies (normal mode rejection) can be achieved by setting the sample window to 100 ms (sample rate to 9.84 sps). The CPU load varies with the input level.
Cypress Semiconductor Corporation
• 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Document Number: 001-13252 Rev. *H Revised May 14, 2013 Document Outline Features and Overview Functional Description Example 1 Example 2 Incremental ADC DC and AC Electrical Characteristics CY8C29xxx Typical Performance Placement Parameters and Resources Example 1 Example 2 Interrupt Generation Control Application Programming Interface ADCINC12_Start ADCINC12_SetPower ADCINC12_Stop ADCINC12_GetSamples ADCINC12_StopAD ADCINC12_fIsDataAvailable ADCINC12_iGetData ADCINC12_ClearFlag Sample Firmware Source Code Configuration Registers Version History
