Simple speedy single-slope (SSSS) ADC biphasic conversion cycle

Authors	Stephen Woodward
Main Document	Article «Simple speedy single-slope ADC»
Description	Figure 1
File Format / Size	PDF / 15 Kb
Document Language	English

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Article «Simple speedy single-slope ADC»

Figure 1. Simple speedy single-slope (SSSS) ADC biphasic conversion cycle
Figure 2. The SSSS ADC waveshapes. The ACQUIRE duration (12 bits) is 90 µs. The INTEGRATE duration is 1 ms max (V_IN·C1/IQ1 = 200 µs/V). Amplitude is 5 Vpp
Figure 3. A1 input buffer unloads V_IN, and R5 calibration trim improves accuracy

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Microcontrollers