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Sleep easy with this desk fan speed reducer

Texas Instruments » 74HCT191, CD4070B

Michael Whybray


Most desk fans I have come across have three speeds: Full Speed, Almost Full Speed, and Off – useless if you want just a gentle air movement, and far too noisy if you are trying to get to sleep (in your bedroom of course, not at your work desk!). The squirrel cage induction motors they use have switches to two or more windings – and possibly a capacitor – to reduce the drive current. But unless the drive frequency is also reduced, the torque and speed stability are poor, so minimal speed reduction is usually available on these fans. Using a triac to provide phase control of the voltage works poorly for the same reason, with the speed very sensitive to the triac firing phase angle and fan load, and has a tendency to stall.

Sleep easy with this desk fan speed reducer
Figure 1. Motor speed controller.

Far better speed stability is obtained by lowering the drive frequency from the standard 50 Hz (or 60 Hz). The main problem is how to do this without spending more than the fan itself cost! The Design Idea shown in Figure 1 achieves this for a few dollars by using a triac to allow only every third half-cycle of the AC mains voltage through to the motor, as shown in Figure 2.

Sleep easy with this desk fan speed reducer
Figure 2. Every third half-cycle.

Although not a continuous sine wave, the fundamental frequency can be seen to be 1/3 of the original mains frequency (60 ms per complete cycle rather than 20 ms), and it drives the motor with smooth impulses of regular spacing and opposite polarity, which keep the motor's internal magnetic field, and hence the rotor, rotating nicely. The result is stable fan operation at a nice low speed which is very much quieter. The usual fan speed control switch settings now have little effect, as the lower drive frequency is the dominant influence on speed.

Looking at Figure 1, R1, D1, D2 and C4 rectify and smooth the incoming 240 VAC mains to provide a low current –5 V supply for the two standard logic circuits: a CD4070B Quad XOR, and a 74HCT191 4-bit counter. The 240 V mains is also fed via R2 to the first XOR gate (wired as a non-inverting buffer) which clips it at –5.6 V and +0.6 V using the built-in input protection circuitry of the IC, then does an almost zero-crossing detection, resulting in a square wave clock at mains frequency. C1 & R2 filter out mains noise and create a time lag about of about 0.4 ms for the clock signal compared to the incoming mains waveform. C2 provides 1 V of dynamic hysteresis over the gate to ensure clean switching, and to reject glitches on the mains and –5 V rail as the triac is triggered.

The clock signal passes through the second XOR buffer stage, which together with its output capacitor C3, provides a delay of about 500 ns. Presenting this with the original clock signal to the inputs of the third XOR gate results in a short positive output pulse every time the incoming clock signal transitions high or low, so we now have a pulse 0.4 ms after every zero-crossing of the mains signal, i.e., every 10 ms (incidentally, a virtue of the venerable 4000-series logic circuits is that you can take liberties like loading the output with a capacitor, as the transistor channel resistance limits the current to a safe value if the supply is under 10 V or so – see page 3 of 4000 Series Logic and Analog Circuitry).

The short positive pulses go to the clock input (CP) of the 74HCT191 binary counter. This is configured to count down (one step every 10 ms) from its Parallel Load value to zero. On reaching zero, the Terminal Count (TC) pin goes high, and causes the voltage across C5 to rise as current flows through R3. On reaching 2.5 V (after about 0.3 ms), the output of the final XOR gate (in this case an inverter) drives counter Parallel Load input ~PL low, forcing a load of the data ‘0011’ on inputs D3-D0. This immediately sets TC low again. The result is that the counter cycles through: 0011, 0010, 0001, and then via a brief visit to 0000, back to 0011.

TC thus pulses high for 0.3 ms, 0.4 ms after every third zero-crossing of the mains. The Ripple Carry output ~RC is the inverse of the TC output (to be exact, very slightly shorter), and when it pulses low for 0.3 ms, it draws current through R4 to trigger the triac. As this occurs alternately during a positive and then a negative cycle of the mains, spaced 30 ms apart, it produces the (idealized) drive waveform in Figure 2. A negative trigger voltage/current is used rather than positive so that the triac is triggered in quadrants II and III, avoiding quadrant IV, which would require a higher drive current (see the 2N6073A data sheet). The 0.4 ms delay from mains zero-crossing means that when the trigger pulse starts and the triac turns on, there is sufficient voltage applied to the inductive motor load to cause current to rise rapidly enough to reach the triac's holding current before the trigger pulse ends. The pulse is limited to 0.3 ms purely to minimize power consumption of the control circuit, which is under 100 mW total.

The snubber network R5/C6 is to prevent unwanted dV/dt retriggering of the triac during commutation with the inductive load. This may not be needed for all fans (mine work fine without it). Use a mains rated capacitor and a bulk rather than film resistor for the snubber. A sensitive gate triac such as the 2N6073A is required so that it can be triggered by the 74HCT series IC, but the ratings of all the other components are low power and not critical on tolerances. The triac will not usually need a heat sink as the fan current, and triac duty cycle, are generally low enough for free air cooling (but do you own calculations!).

With my test fan, the rotation speeds on its own fast and slow settings and nominal mains supply are 31 and 26 rev/s. With the above circuit engaged, the speed drops to 12 rev/s. As a fan's noise is roughly proportional to the 5th power of its speed, it is clear the potential noise reduction is considerable. The residual noise is now partly due to the pulsed nature of the supply waveform which can cause a slight chugging noise; this seems to depend on the angle of the fan and the quality of its bearings and construction.

Finally, by changing the binary number set on the counter data inputs, either with switches or hard-wired, the same circuit can be used to skip even more mains half-cycles, to drop the frequency to 1/5, 1/7…, right down to 1/15 (even multiples do not work as the waveform is one-sided and the motor doesn't rotate). In tests, my fan still ran at these slower speeds, but the chugging effect became annoying and the air movement too low, so I chose to stick with a single speed of 1/3. The lower speeds could be useful in other applications though.

If you build this circuit in a separate box, with a mains socket to plug in an unmodified fan, a simple switch which shorts across MT1 and MT2 of the triac can be used to engage normal fan speed (you can't just set the counter data inputs to 0001 because the inductive load means the load current crosses zero later than the mains voltage, so the next 0.3 ms trigger pulse is mistimed and does not work). To run the circuit with a 120 V 60 Hz supply, simply halve the values of R1 and R2.

p.s., The circuit will also work reliably even if R1 and R2 are connected to the other side of the motor rather than to the mains input. This means the entire circuit becomes a two-terminal black box in series with the fan unit. This makes the wiring simpler, and the off-switch on the fan cuts power to the circuit completely. The value of R1 needs to be reduced to of its original value, as it is only seeing two out of three mains half-cycles to supply the –5 V rail. The circuit still correctly counts mains cycles and delivers the trigger pulses at the right times despite the very distorted waveform now going into R2.

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