Stephen Woodward EDN For at least four decades, dualslope integrating AtoD conversion has formed the core of most every digital multimeter and many industrial and instrumentation applications besides. Elegant in its simplicity, a DSADC (dualslope analogtodigital converter) employs an analog integrator coupled to a comparator and control logic to accumulate (integrate) the input signal, V_{IN}, for a fixed interval, T_{1} – comprising the first “slope” – then to switch the integrator’s input to a fixed negative reference, V_{REF}, to ramp the integrand back to zero – the second “slope” – while measuring the time required to do so, T_{2}. The input voltage is thus:
This Design Idea applies a twist to the familiar algorithm: Simply reversing the order of signal and reference integration results in what I call a reciprocal dualslope integrating ADC (RDSADC). Here, V_{REF} is integrated for a fixed interval, T_{1}. Then the integrator input is switched to –V_{IN}, and the time T_{2} required to ramp back down to zero is measured. Thus:
Given the similar equations, you might reasonably ask: “So what?” So this: In equation 2, the conversion result is inversely proportional to time measurement T_{2 }and therefore to 1/V_{IN}, and differential calculus tells us that the rate of change of inverses varies, not linearly, but as the square of the inverse of the measured value, i.e.,
The payoff is therefore a nonlinear conversion measurement that maintains high resolution for low amplitude inputs without any need for autoranging of the V_{IN} scale factor. A practical implementation of the RDSADC is shown in Figure 1. It converts inputs in the 10bit range of 1 mV to 1 V while maintaining a 10bit resolution at both extremes: 1 mV resolution at V_{IN} = 1 V, and 1 µV resolution at V_{IN} = 1 mV. This translates to a 1,000,000:1, 20bit dynamic range with only a 15bit 32k count resolution for T_{2}. In other words, a 20bit dynamic range is achieved with only a 15bit count, for a 32:1 improvement in conversion time over a similar resolution conventional DSADC. In fact, V_{IN} can go a bit negative, and all the way to 5 V at reduced resolution.
Here’s how it works: The RDSADC cycle begins with connection of V_{REF} to the “+” input of integrator A2 (pin 3) by S1 through the R4/(R3 + R4) voltage divider, and integration during interval T_{1}, ending when V_{2} = V_{REF}, switching comparator A1’s output low (Figure 2).
S1 then lets A2’s “+” input drop nearly to ground (more on that later), while S2 switches A2’s “” input nearly to V_{IN} through R1. V_{2 }then ramps downward at a rate _{nearly }proportional to V_{IN}, defining counting interval T_{2}. Arrival of V_{2 }at the low threshold of A1 terminates T_{2}, completing the ADC cycle and beginning a new one, ad infinitum. About those nearlies: Astute readers will have noticed that during T_{2}, when S1 removes V_{REF} from A1’s “+” input, a 42 mV positive bias is created by R5. The purpose of this bias is to keep A2’s output alive all the way down to the end of the T_{2} slope despite use of a unipolar power supply. Also during T_{2}, R2 creates an effective 32 mV bias^{1}) to ensure that T_{2} remains finite (never more than 32 ms), even when V_{IN} approaches zero. Thus:
This idealized arithmetic ignores realworld tolerances like A1 and A2 input offsets, V_{REF} accuracy, and resistor variations, but these imperfections can be easily compensated computationally with a simple twopoint V_{FULLSCALE} and V_{ZERO} calibration. ^{1)} The 32 mV comes from the R1R2 voltagedivision of the 2.5 V V_{REF} (50 mV), which provides 1.6 µA (32 mV / 20 kΩ) of offset current to the V_{IN} / 20 kΩ input current, minus the “keepalive” bias provided by divider R3R5 (18 mV). Hence 50 mV – 18 mV = 32 mV. Materials on the topic 

