12242009 Compact, fourquadrant lockin amplifier generates two analog outputsAnalog Devices » AD630Generate a pair of quadraturephase digital signals. Stefano Salvatori and Marco Girolami The circuit in this Design Idea realizes a simple, lowcost lockin amplifier employing an Analog Devices AD630 balanced modulatordemodulator IC (Reference 1). The device uses lasertrimmed thinfilm resistors, yielding accuracy and stability and, thus, a flexible commutation architecture. It finds use in sophisticated signalprocessing applications, including synchronous detection. The amplifier can detect a weak ac signal even in the presence of noise sources of much greater amplitude when you know the signal’s frequency and phase.
As an analog multiplier, the AD630 reveals the component of the inputvoltage signal in a narrow band around the frequency of the reference signal. The lowpass filter at the AD630’s output allows you to gain information on the weak signal amplitude, which the uncorrelated noise originally masked. When the input voltage and the reference voltage are in phase, the lowpass filter’s output, V_{OUT}, assumes the maximum amplitude. Conversely, if the input voltage and the reference voltage are in quadrature, the output voltage would ideally be 0V. In this way, if both inphase and quadrature reference signals are available, two balanced demodulators reveal the inphase output voltage to be 0° and the inquadrature output voltage to be 90°. You can calculate the module and phase shift as follows: The two AD630s have a gain of ±2 and receive the amplified signal, V_{IN}, through two identical amplifiers, A_{1} and A_{2}. At Pin 7 of IC_{1}, a bipolar ±5V squared signal appears in phase with the reference signal. OA_{1} integrates the amplifier voltage, which generates a triangular wave that IC_{2}’s comparator compares with the V_{R2} voltage. You must regulate V_{R1} and V_{R2} to obtain a perfect 90°shifted command for IC_{2}. You can monitor the voltage at IC_{2}’s Pin 7. Measurement accuracy and repeatability depend strongly on the RC time constant of the integrator and the values of V_{R1} and V_{R2}.
You can use a different approach to generate inphase and inquadrature reference signals. Figure 2 shows an alldigital circuit, which you can implement in a small CPLD (complex programmablelogic device) to generate the 0 and 90° reference signals in Figure 1. Counter 1 measures the referencesignal time in terms of the N number of digital clock pulses, where the reference time can be different from 50%. It receives a preset command at the N_{1}=1 value at each positive front edge of the reference signal. Dtype flipflop IC_{1} generates such pulses. At each positive edge of the reference signal, IC_{2} acquires the N/4 value. Meanwhile, Counter 2 counts the clock periods and receives a restart command at the N_{2}=1 value when its value reaches the comparatormeasured N/4 quantity.
To overcome the lack of the last EQ signal when the reference time is greater than approximately four times the N/4 integer value, the OR combination of the two RST and EQ pulses yields four almostequidistant positiveedge commands in each referencetime period. The N/4 integer division, a logical right shift by 2 bits of N_{1}, gives a maximum error of three on the last pulse position. These pulses generate the inphase and inquadrature signals, 0 and 90°, respectively, resulting from simple commutations on the positive or negative edges of the signal. Ttype flipflop IC_{3} generates a signal with twice the frequency of the reference signal. In this way, the accuracy is equal to 3/N_{1}. To maintain accuracy at least comparable with that of the AD630, the N_{1} output of Counter 1 would be the highest. However, an increase in the number of bits decreases the maximum reference frequency for a given digitalclock frequency if you want N_{1} to reach high values. For example, if N is 15 bits, the N_{1} output assumes the 32,767 maximum value with an accuracy of approximately 0.01%. If the referencetime period decreases, you can assume a minimum value of 3277—that is, onetenth of the maximum value—for N_{1}, with a correspondingly lower accuracy of 0.1%, which is comparable to the gain accuracy of the AD630. To increase the reference frequency, divide the digital clock’s frequency to select low values when the reference time becomes too long. 

