eSilicon's Custom Cache Memories Meet Performance Target Without Compromising Low Power
eSilicon Corporation and MIPS Technologies announced the tapeout of a high-performance, three-way microprocessor cluster on GLOBALFOUNDRIES' leading-edge, low-power 28nm-SLP process technology. Wafers are currently running in GLOBALFOUNDRIES' Fab 1 in Dresden, Germany, with silicon expected in early 2012. SoC designs can start immediately. MIPS provided the RTL based on its leading-edge MIPS32® 1074KfTM Coherent Processing System (CPS), and eSilicon performed the synthesis and timing-driven layout, optimizing the design to achieve true worst-case performance of 1GHz for the cluster. Typical performance is expected to be approximately 1.5GHz.
To reach the 1GHz target without compromising low power, eSilicon's custom memory team created custom fast cache instances (FCIs) for the L1 caches to replace standard memories that were in the critical path of the design. The 1074Kf CPS is based on the combination of two high-performance technologies-coherent multiprocessing, and the superscalar, Out-of-Order (OoO) MIPS32 74K® processor core as the base CPU. The 74K core is a multi-issue, 15-stage OoO architecture already in production with numerous customers for digital televisions, set-top boxes and a variety of home networking applications. It is broadly used in internet-connected digital home products.
Customers can license the 1GHz implementation from eSilicon today-either as is or customized. The cluster has been taped out as a test chip, and will be offered as a hard macro core. It includes embedded design-for-test (DFT) and design-for-manufacturing (DFM) features so that it can be dropped into a chip design and used without modification. As part of a full SoC development, it can be further customized and optimized to meet the specific needs of the application.
