The readout circuit with sensitive polarity indication
| Authors | Cor van Rij |
| Main Document | Article «A simple circuit to let you characterize JFETs more accurately» |
| Description | Figure 5 |
| File Format / Size | PDF / 16 Kb |
| Document Language | English |
Other Materials from the Main Document
- Article «A simple circuit to let you characterize JFETs more accurately»
- Figure 1. A standard N-JFET drain-source current vs gate-source voltage curve
- Figure 2. A basic, improved circuit for the JFET IDSS and VP measurement
- Figure 3. First implementation of the practical circuit used to measure IDSS and VP
- Figure 4. A circuit with the tailored measurement range that is suited for most JFETs
- Figure 5. The readout circuit with sensitive polarity indication
