The INL is canceled by the TBH topology
| Authors | Stephen Woodward |
| Main Document | Article «Inherently DC accurate 16-bit PWM TBH DAC» |
| Description | Figure 1 |
| File Format / Size | PDF / 13 Kb |
| Document Language | English |
Other Materials from the Main Document
- Article «Inherently DC accurate 16-bit PWM TBH DAC»
- Figure 1. The INL is canceled by the TBH topology
- Figure 2. TBH principle sums two 8-bit PWM signals in one 16-bit DAC = VREF(MSBY+LSBY/256)/256. The asterisked resistors are 0.25% precision types. It is assumed that the PWM frequency (FPWM) is ~10 kHz
- Figure 3. Settling time to full precision requires ~100 PWM cycles = 10 ms for FPWM = 10 kHz