Settling time to full precision requires ~100 PWM cycles = 10 ms for F_PWM = 10 kHz

Authors	Stephen Woodward
Main Document	Article «Inherently DC accurate 16-bit PWM TBH DAC»
Description	Figure 3
File Format / Size	PDF / 12 Kb
Document Language	English

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Article «Inherently DC accurate 16-bit PWM TBH DAC»

Figure 1. The INL is canceled by the TBH topology
Figure 2. TBH principle sums two 8-bit PWM signals in one 16-bit DAC = V_REF(MSBY+LSBY/256)/256. The asterisked resistors are 0.25% precision types. It is assumed that the PWM frequency (F_PWM) is ~10 kHz
Figure 3. Settling time to full precision requires ~100 PWM cycles = 10 ms for F_PWM = 10 kHz

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