The 16-bit DACs are a de facto standard for high DC accuracy and precision domain conversion, but surprisingly few are fully 16-bit (0.0015%) precise. Even when described as “high precision,” some have inaccuracy and integral nonlinearity (INL) that significantly exceed 1 LSB. The TBH PWM-based design detailed here, by contrast, has inherent 16-bit DC accuracy and integral linearity limited only by the quality of the voltage reference. And it gets them without fancy, pricey, high-accuracy components (e.g., no 0.0015% resistors need apply).
Figure 1 shows its underlying nonlinearity-correcting Take-Back-Half (TBH) topology, as explained in: “Take back half improves PWM integral linearity and settling time” (Ref. 1)
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| Figure 1. | The INL is canceled by the TBH topology. |
Figure 1 relies on two differential relationships that effectively subtract out (take back) integral nonlinearity and attenuate ripple.
For signal frequencies less than or equal to the reciprocal of settling time = 1/TS (including DC) XC >> R and
For frequencies greater than or equal to FPWM, XC << R and Z = XRIPPLE – YRIPPLE.
Because only one switch drives node Y while two in parallel drive X, INL due to switch loading at Y is twice that at X.
Therefore, since Z = 2(XAVG – YAVG/2), A1’s differential RC network actively subtracts (takes back) the INL error component, resulting in (theoretically) zero net INL.
Figure 2 illustrates how these elements can fit together in a robust 16-bit DAC circuit design. Here’s how it works.
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| Figure 2. | TBH principle sums two 8-bit PWM signals in one 16-bit DAC = VREF(MSBY+LSBY/256)/256. The asterisked resistors are 0.25% precision types. It is assumed that the PWM frequency (FPWM) is ~10 kHz. |
Two 8-bit resolution PWM signals with a rep rate of ~10 kHz serve as inputs, one for the most significant byte (MSBY) of the setting and the other for the least significant byte (LSBY). The MSBY signal drives R2 and R3, while the LSBY drives the R4, R5, and R7 network. The
ratio of the summing network accommodates the relative significance of the PWM signals. It also enables true 16-bit (15 ppm) conversion precision and differential nonlinearity (DNL) from only 8-bit (2500 ppm) resistor matching.
R6C3 suppresses small nanosecond duration ripple spikes on A1’s output caused by the super-fast output transitions of the U1 switches leaking past A1’s 10 MHz gain-bandwidth product.
The ultimate conversion accuracy is limited almost solely by the 5-V voltage reference quality, so this should be a premium component. Its job is made a little bit (pun) easier by the fact that the maximum current drawn by U1 is a modest 640 µA, which allows for true 16-bit INL with reference impedances up to 0.11 Ω. A maximum reference loading occurs at MSBY duty factor = 50%. The loading falls to near zero at D = 0 and 100%.
The maximum ripple amplitude also occurs at 50%. The output ripple and DAC settling time are illustrated as the red curve in Figure 3.
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| Figure 3. | Settling time to full precision requires ~100 PWM cycles = 10 ms for FPWM = 10 kHz. |
Reference
- Woodward, Stephen. "Take back half improves PWM integral linearity and settling time."