Modern battery-cell voltages of 3 to 3.6 V require circuits that offer efficient low-voltage operation. This Design Idea proposes an ac-coupled instrumentation-amplifier design that features high CMRR (common-mode-rejection ratio), wide dc input-voltage tolerance, and a first-order highpass characteristic. Most of these features stem from a high-gain first-stage design. The circuit uses popular-value and -tolerance components. Figure 1a shows the simplified amplifier circuit. The general principle is that the capacitor, C, and the R_{3 }resistors buffer and ac-couple the input signal. The second stage comprises two differential amplifiers, A_{D}. Each of them amplifies half the differential input signal. A summing operation yields the following expression for V_{OUT}:

In Figure 1a, V_{A}, V_{B}, V_{C}, and V_{D} are the two differential amplifiers' inputs, and A_{D} is the gain. The time constant 2R_{3}C defines the highpass cutoff frequency. Figure 1b shows the detailed circuit. The input stage comprises op amps A_{1}, A_{2}, A_{3}, and A_{4}. A_{1} and A_{2} are the main gain stages. Because their inverting and noninverting inputs are at the same potential, the input voltages supply the R_{3} resistors. The buffers A_{3} and A_{4}, along with the R_{2 }resistors, produce an amplification factor, 1 + R_{3}/R_{2}, for the current in R_{3}, because R_{2 }and R_{3} connect to equal potentials. This circuit structure is the heart of the design. The voltage on capacitor C has no ac component, and A_{1} and A_{2} each amplifies one-half of the differential-input ac signal. C filters the input dc component, which appears at the A_{3} and A_{4} outputs. The second stage is a unity-gain, four-input adder-subtracter stage. It implements the above equation, where

Assuming R_{3} >> R_{2},

Figure 1. |
Capacitor C ac-decouples the simplified amplifier circuit (a); the detailed circuit (b) uses gain stagesand an adder-subtracter stage. |

Another possible implementation for the second stage could use two differential-channel ADCs, producing a digitized V_{OUT}, ready for microcomputer processing. If a ±5 V supply is available, it is possible to obtain V_{OUT} by using two difference amplifiers on one chip, such as the INA2134. You can calculate the minimum CMRR as:

where A_{D(1-4)} is the differential gain of amplifiers A_{1} through A_{4}, A_{CM(1-4)} is the common-mode gain of these amplifiers, A_{D5} is the differential gain of amplifier A_{5}, and A_{CM5 }is the common-mode gain of A_{5}. Δ is the tolerance of the R_{4 }resistors in the circuit. A very important parameter is the op amps' input offset voltage, especially for A_{3} and A_{4}. The A_{1 }and A_{2 }offsets do not contribute to error, because they add to the input signal's dc component, which capacitor C cancels. The maximum output-voltage error attributable to op-amp offset voltage is:

where V_{IOMAX }are the maximum offset voltages of the corresponding op amps. In selecting op amps, you should note the following: A_{3}, A_{4}, and A_{5} should be low-offset and high-CMRR types, and A_{1} and A_{2 }should have high open-loop gain, CMRR, and gain-bandwidth products. Figure 2 shows a practical amplifier circuit. The power supply is one 3 V lithium battery. You can use several op-amp types, such as MCP607s or OPA2336s. Because of the input common-mode voltage range, you set the signal ground to one-third of the supply voltage. The D_{1 }diodes prevent the circuit from latching up. The R_{7}-C_{4} networks provide RF-noise filtering at the inputs. You derive the network's values from the following consideration: With

the high-frequency zero in the amplifier's transfer function cancels:

Figure 2. |
This high-CMRR instrumentation amplifier operates from extremely low supply voltages. |

The circuit has the following advantages:

- The first stage ensures the overall gain, thus providing high CMRR without the use of high-precision resistors in the second stage.
- By connecting the low-frequency-determining RC network to the inverting inputs of the op-amp pair that amplifies the input signal, the circuit needs no additional input buffers.
- The circuit delivers a standard, first-order highpass characteristic, using passive components with popular values and tolerances.
- The differential-input range is as high as 2 V, using a 3 V supply.
- The circuit consumes low supply current and power: approximately 120 μA, 0.4 mW.