Altera Transceiver-Based FPGAs Support New High-Speed System Design Standard

Altera

Stratix GX and Mercury FPGAs Demonstrate High-Bandwidth Performance of Compact Serial Mesh Backplane (CSMB) Standard in Motorola MXP Platform

Altera Corporation and Motorola Computer Group announced that Altera's StratixTM GX and MercuryTM FPGAs support the recently-approved CompactPCI Serial Mesh Backplane (CSMB) specification, a design standard that is intended to facilitate the development of high-bandwidth systems for enterprise, network edge, and next-generation telecom networks. Proposed and pioneered by Motorola Computer Group, CSMB is a point-to-point serial interconnect scalable to more than 700Gb/s that was ratified by the PCI Industrial Computer Manufacturers Group (PICMG) as PICMG 2.20. Motorola's MXP3321 Multi-Service Packet Transport Platform (MXP) product, which addresses the need for telecom OEMs to handle different types of traffic over different networks, relies on Altera FPGAs to provide the high-speed link defined by the CSMB specification.

Altera programmable logic device (PLD) flexibility enables customization to support a wide range of protocols on the line cards in systems that support PICMG 2.20. The next-generation MXP platform will be powered by Altera's Stratix GX family, which offers devices ranging from four to 20 high-speed serial channels at speeds up to 3.125 Gbps and very low power consumption per channel. The Stratix GX family fits the bill in scaling up to a full, high-speed chassis or scaling down to the minimum requirement for a single line card. These devices are available from Altera for any company that wants to develop products that support the PICMG 2.20 specification.

About Stratix GX FPGAs

The Stratix GX family is Altera's second-generation embedded transceiver family based on a 0.13-micron process technology with 1.5-V core voltage. Stratix GX devices have up to 20 embedded 3.125-Gbps transceivers and up to 45 differential I/O pins with dedicated dynamic phase alignment (DPA) capability supporting up to 1-Gbps source-synchronous data transfers. Stratix GX devices also offer up to 41,250 logic elements (LEs), 3.27 Mbits of TriMatrixTM memory, 14 DSP blocks, eight phase locked loops (PLLs), TerminatorTM technology for impedance matching, and signal integrity and advanced I/O buffers capable of interfacing with high-speed memory devices such as DDR SDRAM, QDR SRAM, QDR II SRAM, ZBT SRAM, DDR FCRAM and SDR SRAM devices.

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