Cancel PWM DAC ripple with analog subtraction

Every PWM DAC design needs analog filtering to separate the desired PWM duty-cycle-proportional DC component from unwanted AC ripple. The simplest of these is the basic RC low-pass filter, which gives a peak-to-peak ripple amplitude (for the worst case of 50% PWM duty cycle, where TPWM = PWM cycle time, and assuming RC > TPWM ) of:

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The obvious design tradeoff is that while any desired degree of ripple attenuation can be achieved by choosing a large enough RC product, settling time will correspondingly suffer. For example, if we (fairly logically) choose a definition for the settling band as equal to ripple amplitude, then…

The consequences of this relationship can be illustrated by the 8-bit case:

Given:

Then

which, even for a fairly speedy 32 kHz (31 µs TPWM), predicts a positively glacial 11  ms settling time.

Clearly, if settling time is a critical design parameter, we’ll need to do better and find a less simplistic filtering scheme. The extreme possibilities that lie in this direction are illustrated by my previous DI  [1]

But not every application that can’t tolerate molasses-in-January 355•TPWM settling times need or can justify such a complex filtering solution. The Design Idea presented here addresses these middle-of-the-road applications. As shown in Figure 1, it augments the basic R1/C1 low-pass with an inverter, R2, and C2, which combine to negate and subtract (most of) the undesired AC component from the wanted DC signal, leaving a relatively clean analog output with settling time much less than a simple RC filter.

Схема подавителя пульсаций ШИМ ЦАП и временные диаграммы сигналов.
Figure 1. Waveforms & schematic of PWM DAC ripple canceller.

But how pure is “relatively clean”, and how fast is “much less”? Setting R2 = R1 and C2 = C1, the ripple and settling time figures for the new circuit are:

Referring again to the 8-bit case (illustrated graphically in Figure 1):

Given:

Then:

With a 32 kHz cycle, it’s 16 times faster, with a squared ripple-amplitude ratio!

For many applications, this represents a very worthwhile tradeoff between a modest increase in circuit complexity and a significant increase in PWM DAC performance.

Reference

  1. Stephen Woodward, "Fast-settling synchronous-PWM-DAC filter has almost no ripple"

EDN

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