Capacitor-based charge pumps (or Q-pumps) generally aren’t useful for sourcing large amounts of current, but they work well in niche micropower applications where space is at a premium. They work best in applications where the output voltages are integer multiples of the input voltage. The integer multiples, then, are operating points that result in peak efficiency.
However, Q-pumps can also work well when they are powered from a variable input such as a battery, particularly when quiescent battery drain is more important than heavy-load efficiency. This might be the case when powering a microcontroller that spends most of its time in sleep mode.
Low-voltage microcontrollers such as those in the PIC24 or MSP430 families are generally powered from a regulated supply voltage such as 2.5 V. If clocked slowly, they might draw as little as 25 μA or 50 μA. In standby mode with only the real-time clock running, the current can be vanishingly small, often less than a microamp. This is a good application for the regulated two-stage Q-pump described here, which boosts a single alkaline or nickel-metal-hydride (NiMH) cell to 2.5 V.
This regulated Q-pump has an on-demand oscillator, a feedback regulation loop made from an op amp and reference, and a two-stage pump circuit, plus two flying capacitors, C2 and C4 (Fig. 1). The first pump stage is driven directly by the Touchstone Semiconductor TS12011 comparator, which forms the oscillator, while the second stage is driven by an inverter powered from the output voltage of the first stage. The full-load efficiency varies from 70% to 40% over a 1- to 2.5-V input range, which is comparable to a linear regulator.
The TS12011 analog building block requires very low supply currents (3.2 μA typical ) and operates well down at the sub-1-V levels needed for single-cell operation. The comparator output stage has good drive-current capability down below 0.8 V VDD, an uncommon feature that allows us to drive the first stage directly from the oscillator.
A large hysteresis band was chosen for the oscillator, resulting in a large signal swing on the timing capacitor C6. This achieves the most efficient size-versus-current operating point for the oscillator. The maximum frequency is nominally set at 1 kHz with the component values shown, but can be adjusted up to about 3 kHz, where it becomes limited by the propagation delay through the comparator.
The amount of charge transferred with each cycle and the switching frequency determine the output current. Accurate calculations for the output impedance or output current from a regulated two-stage pump are complex and need a large spreadsheet, but you can make some oversimplifications to get into the right range. Assuming the capacitor is completely charged and discharged with each cycle (which obviously isn’t true), then:
Q = C × V
I = C × V × F
C is the flying capacitor value,
The modified Dickson Multiplier two-stage pump topology used here is a quadrupler, and both stages must be designed to transfer the needed amount of charge at the worst-case low-battery voltage. The first stage is the most important, because the voltage applied to the capacitor is low. Any drop across the first rectifier subtracts from the applied voltage with a resulting loss in headroom, a problem when trying to multiply up to 2.5-V output levels.
(VDD – VFWD – VSAT1) × C3 × F = (0.95 V – 0.2 V – 0.05 V) × 2.2 μF × 1 kHz = 1.5 mA
which is more than sufficient to meet a 50-μA load-current requirement. The best-possible peak-output voltage that you can achieve for the intermediate V1 tap is:
2VDD – 2VFWD – VSAT1(high) – VSAT1(low)
Similarly, the second-stage peak voltage for VOUT is:
2V1 – 2VFWD –VSAT2(high) – VSAT2(low)
Thus, the best-possible peak-load voltage at the minimum input voltage is:
VOUT = 4VDD – 4VFWD – 4VSAT = (4 × 0.95 V) – (4 × 0.2 V) – (2 × 0.05 V) – (2 × 0.1 V) = 2.7 V
where VSAT1 and VSAT2 are the voltage drops across the comparator and the AUP inverter output stages in the ON state, respectively. Again, this analysis is oversimplified but points out the limits of operation.
A NOR-based logic circuit provides non-overlapping gate-drive signals to the synchronous switch. The goal is to be certain that the MOSFET gate is never driven high when the flying capacitor is high. The amount of dead time is set by the 1 MΩ × 47 pF RC time constants. Here, the dead time is very long since the 1-kHz oscillator is so slow.
News on theme: