New Si5348 Clock IC Enables Pervasive Adoption of SyncE and IEEE 1588 Network Synchronization in Internet Infrastructure
Silicon Labs introduced the industry's highest-performance, most cost-effective packet network synchronizer clock. The new Si5348 clock IC combines best-in-class jitter performance with the industry's smallest footprint and lowest power in a highly integrated, standards-compliant solution. The Si5348 clock enables hardware designers to implement a "clock-tree-on-a-chip" solution for Synchronous Ethernet (SyncE), IEEE 1588v2 and general-purpose frequency translation for wireless and telecom infrastructure, broadband networks (e.g., G.fast DSL and PON) and data center applications.
SyncE and IEEE 1588 have become increasingly popular methods to deliver synchronization over packet networks. As these technologies become more widespread, networking equipment designers are demanding more flexible, cost-effective timing solutions that easily integrate into existing hardware architectures. Conventional network synchronizer clocks rely on rigid synchronization clock chip architectures that borrow heavily from legacy Stratum 3 clock ICs, which are not optimized for size, power or performance.
The Si5348 clock delivers a solution that is 50 percent smaller, 35 percent lower power and 80 percent lower jitter than conventional synchronizers. These benefits enable hardware designers to simplify the adoption of packet network synchronization without compromising system-level performance. The Si5348 architecture leverages Silicon Labs' proven fourth-generation DSPLL® technology to deliver best-in-class jitter performance in a timing solution that is fully compliant with IEEE 1588, SyncE and Stratum 3 clocking requirements, enabling the device to be used in a wide variety of timing card and line card clock architectures. The Si5348 clock has been designed to easily interoperate with IEEE 1588 software running on an external host processor, further simplifying system integration.
In packet timing applications, high-stability oscillators play a critical role in defining the network's overall performance in terms of frequency, time and phase accuracy. Network topologies often will dictate the type of temperature-controlled crystal oscillator (TCXO) or oven-controlled crystal oscillator (OCXO) required at each node in the network. The Si5348 clock supports a universal reference input port, enabling the device to be paired with any frequency TCXO/OCXO.
Pricing and Availability
Factory pre-programmed samples and production quantities of the Si5348 network synchronizer clock are available now in a 9 mm × 9 mm QFN package. Si5348 pricing in 10,000-unit quantities ranges from $10.00 to $12.00 (USD), depending on output frequency. Silicon Labs' Si5348-EVB evaluation board, priced at $399 (USD MSRP), enables developers to move quickly from device configuration to detailed performance analysis to custom part number generation in less than five minutes. ClockBuilder Pro software is available from Silicon Labs' website to ease the configuration and evaluation of the Si5348 clock.
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| The Si5348-EVB Evaluation Board. |
Key Features
- Three independent DSPLLs in a single monolithic IC supporting flexible SyncE/IEEE 1588 and SETS architectures
- Meets the requirements of:
- ITU-T G.8273.2 T-BC
- ITU-T G.8262 (SyncE) EEC Options 1 & 2
- ITU-T G.812 Type III, IV
- ITU-T G.813 Option 1
- Telcordia GR-1244, GR-253 (Stratum-3/3E)
- Each DSPLL generates any output frequency from any input frequency
- Input frequency range:
- External crystal: 48-54 MHz
- REF clock: 5-250 MHz
- Diff clock: 8 kHz-750 MHz
- LVCMOS clock: 8 kHz-250 MHz
- Output frequency range:
- Differential: up to 712.5 MHz
- LVCMOS: up to 250 MHz
- Pin or software controllable DCO on each DSPLL w/ typical resolution down to 1 ppt/step
- Excellent jitter performance: <130 fs typ (12 kHz-20 MHz)
- Programmable loop bandwidth per DSPLL: 1 mHz to 4 kHz
- Highly configurable output drivers: LVDS, LVPECL, LVCMOS, HCSL, CML
- Status monitoring: LOS, OOF, LOL
- Serial interface: I2C or SPI (3-wire or 4-wire)
- 5 input, 7 output, 64 pin QFN
- Temperature range: –40 to +85 °C
- Pb-free, RoHS-6 compliant
