We’ve seen lots of interesting conversations and Design Idea (DI) collaboration devising circuits for power switching using inexpensive (and cute!) momentary-contact SPST pushbuttons. A recent and interesting extension of this theme by frequent contributor R Jayapal addresses control of relatively high DC voltages: 48 volts in his chosen case (Ref. 1).
In the course of implementing its high voltage feature, Jayapal’s design switches the negative (VSS a.k.a. “ground”) rail of the incoming supply instead of the (more conventional) positive (VDD) rail. Of course, there’s absolutely nothing physically wrong with this choice (certainly the electrons don’t know the difference!). But because it’s a bit unconventional, I worry that it might create possibilities for the unwary to make accidental, and potentially destructive, misconnections.
Figure 1’s circuit takes a different tack to avoid that.
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| Figure 1. | Flip ON/Flop OFF referenced to the V+ rail. If V+ < 15 V, then set R4 = 0 and omit C2 and Z1. Ensure that C2’s voltage rating is > (V+ – 15 V) and if V+ > 80 V, R4 > 4 V+2. |
Figure 1 returns to an earlier theme of using a PFET to switch the positive rail for power control, and a pair of unbuffered CMOS inverters to create a toggling latch to control the FET. The basic circuit is described in “Flip ON Flop OFF without a Flip/Flop” (Ref. 2).
What’s different here is that all circuit nodes are referenced to V+ instead of ground, and Zener Z1 is used to synthesize a local bias reference. Consequently, any V+ rail up to the limit of Q1’s VDS rating can be accommodated. Of course, if even that’s not good enough, higher rated FETs are available.
Be sure to tie the inputs of any unused U1 gates to V+.
References
- R Jayapal. "Flip ON Flop OFF for 48-VDC systems."
- Woodward, Stephen. "Flip ON Flop OFF without a Flip/Flop."