Introduction
Modern portable electronic devices require a highcapacity Lithiumion battery to power popular features such as highdefinition cameras, edgetoedge highresolution touchscreens and highspeed data connections. As a result, charging power sources like USB TypeC® have increased their output power capabilities to support faster battery charging for highcapacity batteries.
Traditional synchronous buckbased battery chargers cannot take full advantage of high input power because of their maximum efficiency limitations. The challenge for portable electronics designers is how to fit a highefficiency battery charging solution in a small footprint that fully utilizes high input power to achieve fast and cool charging.
A threelevel converter topology that includes added capacitive storage elements and power switches can increase the equivalent switching frequency, f_{SW}, and generate a lower voltage across the inductor, which enables the use of a smaller inductor. This improves total system efficiency, with lower power losses and cooler operating temperatures in a smaller footprint when compared to traditional synchronous buck converters. This article presents an analysis of the threelevel buck topology and provides an operation and powerloss comparison between synchronous buck and threelevel buck battery chargers, including variances in charging current between the three and twolevel buck topologies.
Traditional buck topology
The synchronous twolevel (2L), stepdown (buck) switching topology has been around for decades. A traditional buck switching converter consists of two metaloxide silicon fieldeffect transistors (MOSFETs or FETs), one inductor, an input capacitor in parallel with the input source and an output capacitor, as shown in Figure 1.
Figure 1.  Twolevel (2L) buck switches and gate drive. 
The switch gatedrive signals are complementary, running at duty cycles D and 1 – D. The node between the switches, V_{SW}, alternates between V_{IN} and 0 V; hence the term “twolevel converter.” When Q_{1} is on and Q_{2} is off, the inductor is charging and is providing current to the output. When Q_{2} is on and Q_{1} is off, the inductor discharges to provide current to the output. This produces a fixed dutycycle square waveform that when filtered by the inductor and output capacitor provides an output voltage.
Assuming ideal FETs and continuous inductor current, the steadystate duty cycle is D = V_{OUT}/V_{IN}. The f_{SW }determines the inductor’s inductance, based on V = L × di/dt and rearranged as Equation 1:
(1) 
where K is the inductor current ripple as a percentage of output current, chosen to be 20% to 40%.
For battery charging applications with wide inputvoltage ranges, existing semiconductor processes and inductor technology limit f_{SW} to 1 to 2 MHz. Higher switching frequencies cause transistor switching losses and inductor secondorder AC losses to dominate converter losses. Therefore, when trying to increase converter efficiency and reduce heat dissipation, the common solution is to increase inductor footprint size for a lower DC resistance (DCR).
Threelevel buck operation
The threelevel (3L) buck converter illustrated in Figure 2 is a combination of a switched flying capacitor, C_{FLY}, and a switched inductor circuit, with two additional FETs, Q_{3} and Q_{4}.
Figure 2.  Threelevel (3L) buck switches and gate drive. 
The gatedriving scheme is similar to that of a traditional twophase buck converter. A complementary signal drives the outer FETs, Q_{1} and Q_{2}, with duty cycle D = V_{OUT}/V_{IN}, just like the twolevel (2L) buck converter. A second complementary signal of equal duty cycle drives the inner FETs, Q_{3} and Q_{4}, but is phaseshifted from the outer FET’s signal by 180 degrees. By keeping CFLY balanced at V_{IN}/2, the V_{SW} switch node alternates between V_{IN}, V_{IN}/2 and ground; hence the term “threelevel.”
Figure 3.  Threelevel (3L) converter operation with D less than 0.5. 
Figure 3 shows a complete switching cycle when the duty cycle is less than 0.5 (that is, when the input voltage is more than twice the output voltage). Figure 4 on the next page shows the complete switching cycle when the duty cycle is greater than 0.5.
Figure 4.  Threelevel (3L) converter operation with D greater than 0.5. 
At D = 0.5 (50%), Q_{1} and Q_{4} are on for half of the period; Q_{3} and Q_{2} are on for the other half. This results in V_{SW} remaining at V_{IN}/2, which by definition is equal to V_{OUT}. There is no voltage across the inductor, so the ripple current goes to zero.
Because the FETs are driven 180° out of phase, the switching frequency, f_{SW3L}, at the V_{SW} node is double that of a comparable 2L converter, f_{SW2L}. Each FET only turns on once during the 2L period, therefore T_{SW2L} = 2 × T_{SW3L}.
Threelevel (3L) buck onchip losses
Table 1 compares the 2L buck converter onchip losses, P_{ONCHIP}, to those in the 3L buck converter. Onchip losses include conduction losses from the switches’ resistances, P_{COND}; switching charge losses, P_{OSS} and P_{GATE}; reverse recovery losses, P_{QRR}; currentvoltage losses during gate turnon and turnoff, P_{IV}; and loss across the body diodes during the dead time when both switches are off, P_{DT}. Assuming C_{FLY} is balanced at V_{IN}/2, the 3L buckconverter FETs only need to block half the voltage as compared to the 2L buck converter FETs.
Table 1.  Equations for comparing estimated powerloss  

Making the above assumptions about the 2L and 3L losses enables a theoretical comparison of the onchip power losses between the two topologies as shown in Table 1. The following bullets are highlights from this theoretical comparison:
 The f_{SW} and inductor current ripple are the same for both topologies, which means that the 3L inductance value, L_{3L}, is onefourth that of the 2L, L_{2L}. This is explained more thoroughly in the next section.
 The area allocated for the 2L highside (HS) FET is equal to the sum of the area for the 3L HS FETs (i.e., A_{Q12L} = A_{Q13L }+ A_{Q33L}). With the 3L FETs at onehalf the 2L FET’s voltage rating, the FET resistances are equal (i.e., R_{Q12L} = R_{Q13L} = R_{Q33L}). The same applies to the lowside FETs. This results in the 3L total FET resistance being twice that of the 2L buck for a fixed area.
 If the 3L FETs are at onehalf the voltage of the 2L FET but the 3L FETs are driven with the same transient voltages, dv/dt, at V_{SW}, the turnon and turnoff times are cut in half. This results in P_{IV} being reduced by onehalf.
 Using the same area, the total stored charge remains the same, meaning Q_{OSS(Q1)2L }= Q_{OSS(Q1)3L }+ Q_{OSS(Q3)3L} and it is the same for Q_{OSS(Q2)2L}. The total stored charge is actually less because the 3L FETs are at onehalf the voltage, but this can be ignored in a simple analysis.
As shown in the farright column of Table 1, for the same die area, the 3L topology conduction and deadtime losses double. But because the 3L FETs see onehalf the input voltage compared to the 2L buck, P_{OSS} and P_{IV} losses are halved. An increase in FET area makes it possible to lower conduction losses until switching losses begin to dominate, as shown in Figure 5.
Figure 5.  Onchip losses vs. die area. 
The optimal FET areas, A_{OPT2L} and A_{OPT3L}, occur where switching losses equal conduction losses.