.. increase distortion. Also, be aware that there is a small DC offset when the circuit is on (muting), but at less than 10 mV it can be ignored for the most part, provided the following circuitry is not DC coupled. At worst, it may cause a ...
.. notch filter. To simulate practical variances from the ideal, capacitor values were randomly selected to be within 1% of 10 nF, and R1 and R2 to be within 0.1% of ideal values for a 2400-Hz F OSC . A value of R3 that produced a 130 dB notch ...
.. possible where: as D = 0 to 1. Figure 2. Simple circuit for regulator programming with PWM where V OUT ranges from 0.8 V to 10 V as the duty factor (D) goes from 0 to 1. All that’s required to add PWM control to Figure 1 is to split R 2 ...
.. to allow for the delay in the receiver. An exclusive-OR gate produces a sampling pulse at each bit transition typically, 10% of the data-bit width. This sample pulse samples the raw data the receiver generates, producing clean data. Figure ...
.. generation. The daisy chain of three 1N4001 diodes provides bias for Q2 and Q4. The PWM input frequency is assumed to be 10 kHz or thereabouts. Ripple filtering is the purpose of C1 and C2 and gets some help from an analog subtraction ...
.. precision specification. The combination of C 1 and R 5 implements a lowpass filter with a pole at approximately 10 Hz to remove power-supply noise. The following term describes the performance of IC 2 and its accompanying circuitry: ...
.. G A2 is A2’s gain. Further, Voltage across R1 = Current through R1 = Then, since V A is lightly loaded by A1’s ~10 picoamp (pA) input bias, so R1 can range from hundreds of ohms up to multiple megohms as the application may dictate. ...
.. U2 I/O headroom differential to improve efficiency. As described in the earlier DI (Ref. 1), switches U1b and U1c accept a 10-kHz PWM signal to generate a 0 V to 11.25 V “ADJ” control signal for the U2 regulator via feedback ...
.. 1-A PWM current source. (* = 1% metal film). I OUT = 1.07(D 0.07), I OUT 0. ACMOS inverters U1b through U1f accept a 10 kHz PWM signal to generate a 50 mV to +1.32 V “ADJ” control signal for the U2 current regulator ...
.. for the RC network and other curious connections surrounding the F1a flip/flop. When S1 is pushed and the circuit closed, a 10 ms charging cycle of C1 begins and continues until the 0/1 switching threshold of pin 4 is reached. When that ...