Circuits & Schematics: 1 -Wire Barometer - 5/10 Volt Design vrs 2 - 10

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Search results: 1,580 Output: 91-100   Including: 10 (1091); Design (945); Wire (261); Volt (97); Barometer (3); vrs (0).
  1. .. LM337 Replace the negative V REF with a positive V REF Note the max/min absolute value of 40 V V SET 3 V and 1.5 A I INPUT 10 mA per 317/337 regulator datasheet specs. C1 may be required for dynamic stability. See datasheet recommendations. ...
    .. therefore rise to 0 V, and the internal regulator control amplifier to turn on the internal Darlington pass device. These design equations will then apply: Let V REF 1.25, e.g., 5 When V SET is attained, U1 transitions to a very ...
    24-07-2023
  1. .. delivers almost 1.5 mA at 4.7 V to the auxiliary load. Even at V BATT = 500 mV, the circuit delivers 340 µA into a 10-kΩ load and maintains reasonable LED brightness. Note that IC 1 cannot take power from the auxiliary rail, ...
    .. forward voltages typically ranging from 3 to 5 V, operating them from a single cell presents obvious difficulties. This design exploits the ultralow operating voltage of a single-gate Schmitt inverter, such as the SN74AUC1G14 or the ...
    20-07-2023
  1. .. circuit in Figure 1 is similar in principle to that of a previous Design Idea ( Reference 1 ) but offers improved, more reproducible performance. The output current is almost ...
    19-07-2023
  2. .. voltage for the DAC's reference voltage. The DAC's internal design accommodates ac reference input signals of 10 to +10 V. In this mode, the DAC provides a 5M-sample/sec maximum update rate for one-quarter full-scale code changes ...
    13-07-2023
  3. .. in Figure 1. Note also that the input capacitor and dc/dc regulator input must be able to handle a maximum input voltage of 10 V, resulting from the calculation +V IN1(MAX) + | V IN2(MAX) |. In an event of fault-current conditions, such as ...
    .. sources at 5 V, 300 mA (1.5 W) and 5 V, 300 mA (1.5 W). Because the input uses different-polarity voltage sources, the design uses a flyback dc/dc converter to avoid a system-grounding problem. Level-shifted feedback sensing using a ...
    12-07-2023
  4. .. Note that the signal at V IN1 is from the charging and discharging of C 2 ×R 6 . In this example C 2 is 470 pF, or 10 times larger than the example in Figure 1. When the input pulse is high (after the rising edge), the capacitor ...
    .. signals and negatively for decreasing signals. Figure 3. Differentiator and comparator used for pulse reconstruction. The design in Figure 3 uses a differentiator. Figure 3 also shows the simple gate solution (IC 2 ) for comparison. In ...
    10-07-2023
  5. .. Shannon decoding depends on the accuracy of conversion timing relative to T, as shown in Figure 3, showing the effect of 10% RC value error producing a ~2% = 5 LSB conversion error. This is clearly not compatible with true 8 bit (let alone ...
    .. it relies on electromechanical relays for switching, the archaic technology being attractive because this SD has a 300-volt full scale output. There are of course ways to implement solid state (i.e., fast) switching solutions that can ...
    .. time. Of course, whether “nT” is really fast really depends on how long T really is! Figure 1 presents an SD design in which T = 500 ms (!), making an 8 bit conversion require nT = 8 × 0.5 = 4 seconds! In what ...
    06-07-2023
  6. .. large and energy intensive, so they’re tricky to fit into miniature, power-efficient designs. The thermostat design presented (Figure 1) here can’t eliminate these problems, but it minimizes both. Figure 1. The ...
    04-07-2023
  7. .. for PCs (typically using the popular FTDI or similar chipsets and available fully cabled and connectorized for less than $10) and as internal peripherals in popular microcontroller chips (the TM4C123x contains eight!). Figure 2 The SDD with ...
    .. Figure 2 The SDD with 5V asynchronous serial data, similar to a µC UART output. Figure 2 illustrates an SDD for 5-volt asynchronous serial data of the sort a µC UART might output, and Figure 3 is its timing diagram. ...
    29-06-2023
  8. .. 48.5 97 23.8 79.3 8.5 6.59 77.5 30 410 12.07 56.5 113 27.6 92 12.3 8.92 72.5 T 1 is 200 turns of bifilar AWG 37 enameled wire wound 1-to-1 on a ferrite toroid core. Table 1 shows the experimental results with the voltage doubler and ...
    .. 86.5 3.59 2.75 76.6 15 420 6.02 27.2 136 13.58 90.5 6.3 4.93 78.2 19.4 400 7.37 34.9 145.4 18.33 61.1 7.76 6.19 79.8 25 340 10.47 48.5 97 23.8 79.3 8.5 6.59 77.5 30 410 12.07 56.5 113 27.6 92 12.3 8.92 72.5 T 1 is 200 turns of bifilar AWG 37 ...
    .. circuit in this Design Idea uses an intrinsic property of collector voltages in one-transformer pushpull dc/dc converters: They have ...
    29-06-2023

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