Circuits & Schematics - Digital - 3

Many designs exist for logic-based astable multivibrators, one of the simplest being an RC feedback loop around a single inverting Schmitt trigger inverter (Figure 1). The output charges the capacitor to the upper switching threshold, at which ...

The circuit in Figure 1 allows you to convert capacitance into a pulse train by using a constant current source and a linear monostable formed by two NAND-gate chips ( 74HC132 ). The circuit also provides two pulses to control external counter ...

The performance of the watchdog circuit in Figure 1 may not match that of a dedicated watchdog circuit, but this circuit is helpful when the only watchdog in the lab doesn’t meet your design’s temperature requirement and when you are in ...

Applications ranging from frequency counting and synthesis to sensor signal conditioning require conversion of RF signals to digital-logic levels. In such situations, designers typically use a high-speed voltage comparator to perform the ...

In this Design Idea, we look at how electromechanical relays display hysteresis behavior that is surprisingly similar to the solid-state Schmitt trigger circuits, and how they can be used for many similar applications. This Design Idea is inspired ...

Digital-system designs require you to consider many core voltages. Memory operates at 1.8 V, I 2 C and FPGA devices operate at 3.3 V, microcontrollers operate at 5 V, and charge-coupled-device image sensors operate at 9 to 8 V. Clocks for each ...

The circuit in Figure 1 uses the LM358 dual op amp running as a comparator, plus a few other inexpensive components, to make a TTL (transistor- transistor-logic)/CMOS-logic probe. The circuit gets its power from the circuit under test, which lets ...

The circuit in Figure 1 produces a single debounced pulse each time you press S 1 . Moreover, the circuit uses only logic power from the remote pull-up resistor, R 2 . You can use the circuit to detect when a key is pressed in a nonenergized ...

Amplifiers with positive feedback are the bases of signal-grade pulse-forming circuits. This setup ensures a triggerlike operation in which the input signal crosses the input-threshold level; in most cases, the input signal is a voltage signal. The ...

Today's digital delay lines can process pulses no shorter than their delay times, and that restriction confines the devices to applications in which the duty cycle remains near 50%. A limited range of available delays (2 to 100 nsec per tap) ...