.. on the comparison match of a preset count. You base the count on the desired frequency output and the timer's internal clock rate. You then adjust the output of the microcontroller's timer to remove offset. You need to eliminate as ...
.. fed circuit, reduces gain TC to 8 ppm/ C and achieves 15 ppm linearity by replacing the capacitor with a quartz-stabilized clock. Figure 1. 5 V powered, quartz-stabilized 10 kHz V-F converter has 0.0015% linearity and 8 ppm/ C temperature ...
.. The demodulator DC output is buffered by chopper stabilized A2 which provides the circuit output. A2’s internal 1 kHz clock, level shifted by Q2, drives the CD4040 frequency divider. One divider output supplies the 0.5 Hz square wave; ...
.. LTC6943 -based charge pump. The charge pump’s two sections operate out-of-phase, resulting in charge transfer at each clock transition. Charge pump stability is primarily determined by the LT1460 2.5 V reference, the switches low ...
.. that comes with asynchronous preset and clear inputs because they have the same function as the set/reset inputs when the clock and data inputs are grounded. This method functions only with CMOS-logic families that offer the benefits of ...
.. switching regulator to form a high voltage switched mode control loop. The LT1072 pulse width modulates Q1 at its 40 kHz clock rate. L1’s inductive events are rectified and stored in the 2 µF output capacitor. The 1 MΩ ...
.. signal to the same duty cycle as the 1-kHz input signal. The time constants of these filters should be much longer than the clock period to minimize duty-cycle jitter. You use a 500-msec time-constant network for the 1-kHz PWM signal and a ...
.. amplifier becomes The output voltage is Both the input voltage and the digital-input data can be time variables, and the clock frequency for fetching digital-input data can be as high as 50 MHz. Figure 1. The resistive DAC-potentiometer ...
.. V output can be conveniently converted to a digital temperature readout by standard microcontroller timer hardware. At a clock rate of 1 MHz, conversion resolution over one oscillation half-cycle period T is 0.1 . A typo apparently ...
.. 3 shows the second part of the control circuit located at the lamps' site. Signals V 3 and V 4 in Figure 2 drive the clock input of toggle flip-flops IC 1A and IC 1B , respectively. For clarity, Figure 3 doesn't show the ...