Circuits & Schematics: 10 - 3

Search for: "10"
Search results: 1,187 Output: 21-30
  1. Stephen Woodward
    .. The asterisked resistors are 1% or better and R S = 1.25 Ω. The 5-Vpp PWM input has a frequency (F PWM ) assumed to be 10 kHz or thereabouts. If it doesn’t, scale C 1 appropriately with: The resulting PWM switching of Q 2 creates a ...
    Apr 16, 2025
  1. David Lees Donald Schelle
    Circuits Microcontrollers Usage Fairchild FDN359AN FDS6679 QSE113
    .. you should choose the part-number option according to your application. The maximum data rate (determined by Q1) exceeds 10 kbps. Materials on the topic Datasheet Fairchild FDN359AN Datasheet Fairchild FDS6679 Datasheet Fairchild QSE113 ...
    Apr 15, 2025
  1. Tim Davis
    Circuits Measurement Analog Devices AD8220 ADR5041 LT1634 LT3081 REF195
    .. The crystal clock’s supply is powered with 5 V from the REF195. The clock’s output will swing between 5 and 10 V with respect to ground. The level-shifted clock is applied to the comparator’s inverting terminal. The ...
    Apr 9, 2025
  2. Stephen Woodward
    .. out that Figure 3 will work. Figure 3. Do something useful with the other 2/3rds of U1, eliminate Q1 for loads of less than 10 mA, and gain short-circuit protection for free. R ON for the 4069 is V+ dependent but can range as low as 200 Ω ...
    Apr 7, 2025
  3. Mike Wong Tamara A. Papalias
    .. resistor with 1.0 V V GS threshold. It is fully on when the input is below 4.2 V. When the input is greater than 4.2 V, pin 10 of the boost converter needs to rise above the input voltage. Therefore, the voltage divider of R 5 and R 6 begins to ...
    Apr 3, 2025
  4. Rod Elliott
    .. increase distortion. Also, be aware that there is a small DC offset when the circuit is on (muting), but at less than 10 mV it can be ignored for the most part, provided the following circuitry is not DC coupled. At worst, it may cause a ...
    Apr 1, 2025
  5. Christopher Paul
    .. notch filter. To simulate practical variances from the ideal, capacitor values were randomly selected to be within 1% of 10 nF, and R1 and R2 to be within 0.1% of ideal values for a 2400-Hz F OSC . A value of R3 that produced a 130 dB notch ...
    Mar 7, 2025
  6. Stephen Woodward
    .. possible where: as D = 0 to 1. Figure 2. Simple circuit for regulator programming with PWM where V OUT ranges from 0.8 V to 10 V as the duty factor (D) goes from 0 to 1. All that’s required to add PWM control to Figure 1 is to split R 2 ...
    Mar 7, 2025
  7. Israel Schneiderman
    Circuits Digital Texas Instruments LM393 SN74HC74 SN74HC86
    .. to allow for the delay in the receiver. An exclusive-OR gate produces a sampling pulse at each bit transition typically, 10% of the data-bit width. This sample pulse samples the raw data the receiver generates, producing clean data. Figure ...
    Mar 4, 2025
  8. Stephen Woodward
    .. generation. The daisy chain of three 1N4001 diodes provides bias for Q2 and Q4. The PWM input frequency is assumed to be 10 kHz or thereabouts. Ripple filtering is the purpose of C1 and C2 and gets some help from an analog subtraction ...
    Mar 4, 2025

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